What Works Best For Chiplets

By Anne Meixner - 18 Apr, 2024 - Comments: 0

The semiconductor industry is preparing for the migration from proprietary chiplet-based systems to a more open chiplet ecosystem, in which chiplets fabricated by different companies of various technologies and device nodes can be integrated in a single package with acceptable yield. To make this work as expected, the chip industry will have to solve a variety of well-documented technical an... » read more

Fan-Out Panel-Level Packaging Hurdles

By Anne Meixner - 24 Jan, 2024 - Comments: 0

Fan-out panel-level packaging (FOPLP) promises to significantly lower assembly costs over fan-out wafer-level packaging, providing the relevant processes for die placement, molding and redistribution layers (RDLs) formation can be scaled up with equivalent yield. There is still much work to be done before that happens. Until now, FOPLP has been adopted for devices that are manufactured in ve... » read more

Many More Hurdles In Heterogeneous Integration

By Laura Peters - 18 Jan, 2024 - Comments: 0

Advanced packaging options continue to stack up in the pursuit of “More than Moore” and higher levels of integration. It has become a place where many high-density interconnects converge, and where many new and familiar problems need to be addressed. The industry’s first foray into fine-pitch multi-die packaging utilized silicon interposers with through-silicon vias (TSVs) to deliver s... » read more

Reducing Advanced Packaging Costs

By Ed Sperling - 09 Jan, 2019 - Comments: 0

Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

The Process Design Kit: Protecting Design Know-How

By John Ferguson - 08 Nov, 2018 - Comments: 2

Once upon a time, integrated circuits (ICs) were built by the same companies that designed them. The design of an IC was tightly integrated with the manufacturing processes available within each company. In these days, when designs contained hundreds of transistors, companies modeled each feature in an IC at a first principles level, meaning each transistor or fundamental device was analyzed an... » read more

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Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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What Works Best For Chiplets

Fan-Out Panel-Level Packaging Hurdles

Many More Hurdles In Heterogeneous Integration

Reducing Advanced Packaging Costs

The Process Design Kit: Protecting Design Know-How

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