tag: advanced packaging

Electromagnetic Simulation And 3D-IC Interposers
By Matt Commens - 11 Jul, 2022 - Comments: 0

By Matt Commens, Juliano Mologni, and Pete Gasperini Today’s 3D integrated circuit (3D-IC) technology is the culmination of 40 years of research in universities and laboratories scattered across the globe. Beginning with dynamic random-access memory (DRAM) deployments that appeared on the market a decade ago, 3D-IC has since expanded its reach. It is now decisively beginning to achieve the... » read more

Delay-based PUF for Chiplets to Verify System Integrity
By Technical Paper Link - 08 Jul, 2022 - Comments: 0

New technical paper titled "Know Time to Die – Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs" by researchers at University of Massachusetts, Amherst MA, Abstract (partial): "In this paper we propose a delay-based PUF for chiplets to verify system integrity. Our technique allows a single chiplet to initiate a protocol with its neighbors to measure un... » read more

Security Risks Widen With Commercial Chiplets
By Ed Sperling - 07 Jul, 2022 - Comments: 0

The commercialization of chiplets is expected to increase the number and breadth of attack surfaces in electronic systems, making it harder to keep track of all the hardened IP jammed into a package and to verify its authenticity and robustness against hackers. Until now this has been largely a non-issue, because the only companies using chiplets today — AMD, Intel, and Marvell — interna... » read more

EDA Gaps At The Leading Edge
By Ed Sperling - 29 Jun, 2022 - Comments: 1

Semiconductor Engineering sat down to discuss why new approaches are required for heterogeneous designs, with Bari Biswas, senior vice president for the Silicon Realization Group at Synopsys; John Lee, general manager and vice president of the Ansys Semiconductor business unit; Michael Jackson, corporate vice president for R&D at Cadence; Prashant Varshney, head of product for Microsoft Azu... » read more

Week In Review: Manufacturing, Test
By Ed Sperling - 17 Jun, 2022 - Comments: 0

Node scaling wars are revving up, although much of the action is happening where most people can't see it — inside of research labs. This is difficult stuff, which makes delivery dates difficult to pinpoint, and no one wants to give away their competitive position or commit to a timeline they can't keep. Billions of dollars of leading-edge research — funded by pure-play foundry TSMC, IDM... » read more

Variation Making Trouble In Advanced Packages
By Ed Sperling - 16 Jun, 2022 - Comments: 2

Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when. Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-t... » read more

Chipmaking In The Third Dimension
By Krishnan Shrinivasan - 16 Jun, 2022 - Comments: 0

Every few months, new and improved electronics are introduced. They’re typically smaller, smarter, faster, have more bandwidth, are more power-efficient, etc. — all thanks to a new generation of advanced chips and processors. Our digital society has come to expect this steady drip of new devices as sure as the sun will rise tomorrow. Behind the scenes, however, engineers are working feve... » read more

Audio, Visual Advances Intensify IC Design Tradeoffs
By Ann Mutschler - 13 Jun, 2022 - Comments: 0

A spike in the number of audio and visual sensors is greatly increasing design complexity in chips and systems, forcing engineers to make tradeoffs that can affect performance, power, and cost. Collectively, these sensors generate so much data that designers must consider where to process different data, how to prioritize it, and how to optimize it for specific applications. The tradeoffs in... » read more

DRAM Thermal Issues Reach Crisis Point
By Karen Heyman - 09 Jun, 2022 - Comments: 5

Within the DRAM world, thermal issues are at a crisis point. At 14nm and below, and in the most advanced packaging schemes, an entirely new metric may be needed to address the multiplier effect of how thermal density increasingly turns minor issues into major problems. A few overheated transistors may not greatly affect reliability, but the heat generated from a few billion transistors does.... » read more

Center Stage: The Time For Hybrid Bonding Has Arrived
By Woo Young Han - 07 Jun, 2022 - Comments: 0

When the subject of hybrid bonding is brought up in the industry, the focus is often on how this technique is used to manufacture CMOS image sensors (CIS), an essential device for today’s digital cameras, particularly those found in smartphones. As such, CIS is a common touchpoint given the ubiquity of mobile phones, whether you hold a product from Apple, Samsung, or Huawei in your hands. ... » read more

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