tag: advanced packaging

Geopolitical And Economic Outlook For Chips And Equipment
By Ed Sperling - 17 Jun, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss geopolitical and economic changes and how they affect the chip industry with Jean-Christophe Eloy, CEO of Yole Developpement; Risto Puhakka, president of VLSI Research; Carolyn Evans, chief economist at Intel; Duncan Meldrum, chief economist at Hilltop Economics; and Rozalia Beica, head of the semiconductor business at AT&S... » read more

Thermal Floorplanning For Chips
By Brian Bailey - 10 Jun, 2021 - Comments: 0

Heat management is becoming crucial to an increasing number of chips, and it's one of a growing number of interconnected factors that must be considered throughout the entire development flow. At the same time, design requirements are exacerbating thermal problems. Those designs either have to increase margins or become more intelligent about the way heat is generated, distributed, and dissi... » read more

Characterization Of CMP Processes With White Light Interferometry
By Bruker - 08 Jun, 2021 - Comments: 0

Faster computer and electronic processors require smaller features for integrated circuits (IC), which in turn require smaller and smoother substrate surfaces. Chemical mechanical polishing (CMP) has become one of the most critical semiconductor fabrication technologies because it offers a superior means of removing unwanted topography in interlevel dielectric layers and achieving sufficient pl... » read more

Monitoring Performance From Inside A Chip
By Ed Sperling - 01 Jun, 2021 - Comments: 0

Deep data, which is generated inside the chip rather than externally, is becoming more critical at each new process node and in advanced packages. Uzi Baruch, chief strategy officer at proteanTecs, talks with Semiconductor Engineering about using that data to identify potential problems before they result in failures in the field, and why it's essential to monitor these devices throughout their... » read more

The Increasingly Uneven Race To 3nm/2nm
By Mark LaPedus and Ed Sperling - 24 May, 2021 - Comments: 2

Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult. It's also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance an... » read more

Advanced Packaging’s Next Wave
By Mark LaPedus - 20 May, 2021 - Comments: 0

Packaging houses are readying the next wave of advanced packages, enabling new system-level chip designs for a range of applications. These advanced packages involve a range of technologies, such as 2.5D/3D, chiplets, fan-out and system-in-package (SiP). Each of these, in turn, offers an array of options for assembling and integrating complex dies in an advanced package, providing chip custo... » read more

Chiplets: A Solution For The Shortage Of Chips
By Andy Heinig - 13 May, 2021 - Comments: 1

These days, there are new reports on the shortage of chips almost every day. Currently, this issue is affecting mainly car manufacturers such as Audi, Ford, and more. But other system manufacturers, such as in the machine construction industry, are also facing this challenge. Even manufacturers of mass-produced articles such as game consoles are reporting the same problems. The problem is sure ... » read more

In-Chip Sensing And PVT Monitoring: Not Just An Insurance Policy
By Ramsay Allen - 11 May, 2021 - Comments: 0

You wouldn’t drive an expensive car without insurance or take a flight in an aircraft without performing instrument and control surface checks. So why would you take the risk of designing a multi-million dollar advanced node semiconductor device without making sure you are aware of, and able to manage, the dynamic conditions that had the potential to make or break a silicon product? Advanced... » read more

Testing Analog Circuits Becoming More Difficult
By Susan Rambo - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Steep Spike For Chip Complexity And Unknowns
By Ed Sperling - 05 May, 2021 - Comments: 0

Cramming more and different kinds of processors and memories onto a die or into a package is causing the number of unknowns and the complexity of those designs to skyrocket. There are good reasons for combining all of these different devices into an SoC or advanced package. They increase functionality and can offer big improvements in performance and power that are no longer available just b... » read more

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