tag: advanced packaging

Why Scaling Must Continue
By Ed Sperling - 15 Aug, 2019 - Comments: 3

The entire semiconductor industry has come to the realization that the economics of scaling logic are gone. By any metric—price per transistor, price per watt, price per unit area of silicon—the economics are no longer in the plus column. So why continue? The answer is more complicated than it first appears. This isn't just about inertia and continuing to miniaturize what was proven in t... » read more

Speed Returns As The Key Metric
By Ed Sperling - 08 Aug, 2019 - Comments: 0

For the foreseeable future, it's all about performance. For the past decade or so, power and battery life have been the defining characteristics of chip design. Performance was second to those. This was particularly important in smart phones and wearable devices, where time between charges was a key selling point. In fact, power-hungry processors killed the first round of smart watches. But ... » read more

Using Better Data To Shorten Test Time
By Ed Sperling - 06 Aug, 2019 - Comments: 1

The combination of machine learning plus more sensors embedded into IC manufacturing equipment is creating new possibilities for more targeted testing and faster throughput for fabs and OSATs. The goal is to improve quality and reduce the cost of manufacturing complex chips, where time spent in manufacturing is ballooning at the most advanced nodes. As the number of transistors on a die incr... » read more

Cloudy Outlook Seen For IC Biz
By Mark LaPedus - 29 Jul, 2019 - Comments: 0

After a slowdown in the first half of 2019, chipmakers and equipment vendors face a cloudy outlook for the second half of this year, with a possible recovery in 2020. Generally, the semiconductor industry began to see a slowdown starting in mid- to late-2018, which extended into the first half of 2019. During the first half of this year, memory and non-memory vendors were negatively impacted... » read more

Low-Power Design Becomes Even More Complex
By Ann Mutschler - 16 Jul, 2019 - Comments: 0

Throughout the SoC design flow, there has been a tremendous amount of research done to ease the pain of managing a long list of power-related issues. And while headway has been made, the addition of new application areas such as AI/ML/DL, automotive and IoT has raised as many new problems as have been solved. The challenges are particularly acute at leading-edge nodes where devices are power... » read more

Rethinking What Goes On A Chip
By Ed Sperling - 27 Jun, 2019 - Comments: 0

There are hints across the chip industry that chipmakers are beginning to reexamine one of the basic concepts of chip design. For more than 50 years, progress in semiconductors was measured by the ability to double the density of transistors on a piece of silicon. While that approach continues to be useful, the power and performance benefits have been dwindling for the past couple of nodes. ... » read more

Automation And Correct By Construction Will Empower 3D-IC Adoption
By Youngsoo Lee - 27 Jun, 2019 - Comments: 0

When research on 3D ICs was in full swing around 2009, I had been researching on how through-silicon-via (TSV) was related to thermal in a semiconductor chip-making company, and it seemed logical that 3D ICs would become mainstream. However, during the past 10 years, use of 3D stacked die has been applied to only a few applications, such as memory or image sensors, and the 2.5D solution using i... » read more

What’s Next In Advanced Packaging
By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Why Chips Are Getting Noisier
By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

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