tag: advanced packaging

What’s The Best Advanced Packaging Option?
By Mark LaPedus - 17 Oct, 2019 - Comments: 2

As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

Process To Produce High Aspect Ratio Electroplated Copper Pillars On 300 mm Wafers
By Veeco - 16 Oct, 2019 - Comments: 0

This work provides details of a complete and partially optimized process to manufacture high aspect ratio copper pillars with heights of up to 80 µm on 200 and 300 mm wafers. Across wafer uniformity data for all materials and process steps are given. Results will show excellent resist adhesion on copper and electroplating durability. Cross sectional SEM analysis of resist and electroplated pil... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Less Margin, More Respins, And New Markets
By Ed Sperling - 10 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS' Semiconductor Business Unit; Simon Burke, distinguished engineer at Xilinx; Duane Boning, professor of electrical engineering and computer science at MIT; and Thomas Harms, director EDA/IP Alliance at Infineon. What foll... » read more

Reducing Costly Flaws In Heterogeneous Designs
By Ed Sperling - 08 Oct, 2019 - Comments: 0

The cost of defects is rising as chipmakers begin adding multiple chips into a package, or multiple processor cores and memories on the same die. Put simply, one bad wire can spoil an entire system. Two main issues need to be solved to reduce the number of defects. The first is identifying the actual defect, which becomes more difficult as chips grow larger and more complex, and whenever chi... » read more

More Data, More Processing, More Chips
By Ed Sperling - 07 Oct, 2019 - Comments: 0

Simon Segars, CEO of Arm, sat down with Semiconductor Engineering to talk about the impact of heterogeneous computing and new packaging approaches on IP, the need for more security, and how 5G and the edge will impact compute architectures and the chip industry. SE: There are a whole bunch of new markets opening up. How does Arm plan to tackle those? Segars: Luckily for us, we can design ... » read more

Driving With Chiplets
By Andy Heinig - 24 Sep, 2019 - Comments: 0

The first examples of the upper class of vehicles that can drive autonomously on the highway already have arrived on the market or will be introduced to the market in the coming years. Travel on the highway was selected as the first application because the number of objects that have to be taken into account in front of, next to, and behind the vehicle is manageable. This means the required ... » read more

Stacking Memory On Logic, Take Two
By Ed Sperling - 19 Sep, 2019 - Comments: 1

True 3D-ICs, where a memory die is stacked on top of a logic die using through-silicon vias, appear to be gaining momentum. There are a couple reasons why this is happening, and a handful of issues that need to be considered before even seriously considering this option. None of this is easy. On a scale of 1 to 10, this ranks somewhere around 9.99, in part because the EDA tools needed to rem... » read more

Another Brick Or Two In The Chip Design Wall
By Ed Sperling - 12 Sep, 2019 - Comments: 1

Physical challenges come and go in the semiconductor world. But increasingly, they also stick around, showing up in inconvenient places at the worst time. The chip industry has confronted and solved some massive challenges over the years. There was the 1 micron lithography wall, which was supposed to be impenetrable. That was followed by the 193nm litho challenge, which cost many billions of... » read more

3D Power Delivery
By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

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