A Node Too Far?


Physics is an unforgiving master. While the semiconductor industry has been actively developing new transistor structures, new materials for interconnects and lining trenches, and new approaches to alleviate congestion at the lowest metal levels, it also has been playing an accelerating game of Whac-a-Mole. Whenever a problem pops up, the solution to that problem is never complete and more prob... » read more

Using Big Data For Yield And Reliability


John O’Donnell, CEO of yieldHUB, talks about the importance of clean data for traceability, yield improvement and device reliability, where and how it gets cleaned, and why that needs to be accompanied by domain expertise. » read more

Making Chips At 3nm And Beyond


Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

The Convergence Of Advanced Packaging And SMT


One statement is almost always true in the electronics industry: smaller is better. The relentless demand for electronic systems that pack more computing power and functionality into less space has driven the development of new processes and designs since the invention of the integrated circuit. In recent years that drive has taken a new direction, literally, as manufacturers have discovered th... » read more

The Need For Traceability In Auto Chips


Someday your car will drive itself to a repair shop for a recall using a scheduling application that is both efficient and can prioritize which vehicles need to be fixed first. But that's still a ways off. Proactive identification of issues is not yet available. To be ready for that, today’s data analytics systems need to begin supporting targeted recalls, enabling predictive maintenance a... » read more

The Story Behind Advanced Packaging, Heterogeneous Integration and Test


The introduction of AMD’S FIJI chip a few years ago marked an important technology turning point for the semiconductor industry. This revolutionary graphics product delivered capability and innovation by relying on the first commercial example of 2.5D heterogenous integration, featuring a GPU assembled with High-Bandwidth-Memory (HBM) using Through-Silicon-Via (TSV) interconnect and interpose... » read more

Packaging And Package Design For AI At The Edge


Industrial applications will acquire significantly more data directly from machines in coming years. To properly handle this increase in data, it must already be prepared at the machine. The data of the individual sensors can be processed, or an initial data merger can take place here at the so-called “edge.” Algorithms and methods from the field of artificial intelligence increasingly a... » read more

Test Costs Spiking


The cost of test is rising as a percentage of manufacturing costs, fueled by concerns about reliability of advanced-node designs in cars and data centers, as well as extended lifetimes for chips in those and other markets. For decades, test was limited to a flat 2% of total manufacturing cost, a formula developed prior to the turn of the Millennium after chipmakers and foundries saw the traj... » read more

Grading Chips For Longer Lifetimes


Figuring out how to grade chips is becoming much more difficult as these chips are used in applications where they are supposed to last for decades rather than just a couple of years. During manufacturing, semiconductors typically are run through a battery of tests involving performance and power, and then priced accordingly. But that is no longer a straightforward process for several reason... » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages


Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

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