tag: advanced packaging

Low-Power Design Becomes Even More Complex
By Ann Mutschler - 16 Jul, 2019 - Comments: 0

Throughout the SoC design flow, there has been a tremendous amount of research done to ease the pain of managing a long list of power-related issues. And while headway has been made, the addition of new application areas such as AI/ML/DL, automotive and IoT has raised as many new problems as have been solved. The challenges are particularly acute at leading-edge nodes where devices are power... » read more

Rethinking What Goes On A Chip
By Ed Sperling - 27 Jun, 2019 - Comments: 0

There are hints across the chip industry that chipmakers are beginning to reexamine one of the basic concepts of chip design. For more than 50 years, progress in semiconductors was measured by the ability to double the density of transistors on a piece of silicon. While that approach continues to be useful, the power and performance benefits have been dwindling for the past couple of nodes. ... » read more

Automation And Correct By Construction Will Empower 3D-IC Adoption
By Youngsoo Lee - 27 Jun, 2019 - Comments: 0

When research on 3D ICs was in full swing around 2009, I had been researching on how through-silicon-via (TSV) was related to thermal in a semiconductor chip-making company, and it seemed logical that 3D ICs would become mainstream. However, during the past 10 years, use of 3D stacked die has been applied to only a few applications, such as memory or image sensors, and the 2.5D solution using i... » read more

What’s Next In Advanced Packaging
By Mark LaPedus - 20 Jun, 2019 - Comments: 3

Packaging houses are readying the next wave of advanced IC packages, hoping to gain a bigger foothold in the race to develop next-generation chip designs. At a recent event, ASE, Leti/STMicroelectronics, TSMC and others described some of their new and advanced IC packaging technologies, which involve various product categories, such as 2.5D, 3D and fan-out. Some new packaging technologies ar... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Why Chips Are Getting Noisier
By Brian Bailey - 13 Jun, 2019 - Comments: 4

In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not mean that it can be ignored anymore. With Moore's Law slowing, designs have to do more with less. Margins are being squeezed, additional concurrency is added, and attempts are made to opti... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

Test Moving Forward And Backward
By Ed Sperling - 11 Jun, 2019 - Comments: 0

Test, once considered an important but rather mundane way of separating good chips from the not-so-good and the total rejects, is taking on a whole new life. After decades of largely living in the shadows behind design and advancements in materials and lithography, test has quietly shifted into a much more critical and more public role. But it has taken several rather significant shifts acro... » read more

Meltdown, Spectre And Foreshadow
By Ed Sperling - 03 Jun, 2019 - Comments: 0

Ben Levine, senior director of product management for Rambus’ Security Division, talks with Semiconductor Engineering about hardware-specific attacks, why they are so dangerous, and how they work. » read more

Partitioning In 3D
By Katherine Derbyshire - 23 May, 2019 - Comments: 2

The best way to improve transistor density isn't necessarily to cram more of them onto a single die. Moore’s Law in its original form stated that device density doubles about every two years while cost remains constant. It relied on the observation that the cost of a processed silicon wafer remained constant regardless of the number of devices printed on it, which in turn depended on litho... » read more

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