tag: advanced packaging

Chiplet Momentum Builds, Despite Tradeoffs
By Brian Bailey - 13 May, 2019 - Comments: 0

Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent 'chiplet' market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness. Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semico... » read more

Raising The Abstraction Level For Power
By Brian Bailey - 09 May, 2019 - Comments: 0

Power-aware design is still a relatively new concern for many semiconductor products, and since inception it has changed several times and in different ways. Initially people were concerned about peak power. Today, they care about peak, total energy, thermal and other effects. The industry has tried several abstractions ranging from system-level analysis, which promised to swamp implementati... » read more

Focus Shifting From 2.5D To Fan-Outs For Lower Cost
By Ed Sperling - 29 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

Lithography Options For Next-Gen Devices
By Mark LaPedus - 18 Apr, 2019 - Comments: 2

Chipmakers are ramping up extreme ultraviolet (EUV) lithography for advanced logic at 7nm and/or 5nm, but EUV isn’t the only lithographic option on the table. For some time, the industry has been working on an assortment of other next-generation lithography technologies, including a new version of EUV. Each technology is different and aimed at different applications. Some are here today, w... » read more

More Memory And Processor Tradeoffs
By Ed Sperling - 11 Apr, 2019 - Comments: 0

Creating a new chip architecture is becoming an increasingly complex series of tradeoffs about memories and processing elements, but the benefits are not always obvious when those tradeoffs are being made. This used to be a fairly straightforward exercise when there was one processor, on-chip SRAM and off-chip DRAM. Fast forward to 7/5nm, where chips are being developed for AI, mobile ph... » read more

Multi-Physics At 5/3nm
By Ed Sperling - 11 Apr, 2019 - Comments: 0

Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes more critical as designs shrink from 7nm to 5nm and eventually to 3nm. In addition, more chips are being customized, and more of those chips are part of broader systems that may involve an AI com... » read more

Billion-Gate Design Connectivity
By Ed Sperling - 27 Mar, 2019 - Comments: 0

Sasa Stamenkovic, senior field application engineer at OneSpin Solutions, explains how to find and resolve connectivity issues in integrating large numbers of components in very big designs, often at the leading edge nodes and in markets such as AI. » read more

A Different Kind Of Material World
By Ed Sperling - 21 Mar, 2019 - Comments: 1

The semiconductor manufacturing world is poised for big change, and the driver will be materials. Materials always have been a critical factor in semiconductors. Silicon is so important that an entire region of California is named after it. Rare earths have raised fears about nationalistic monopolies. And the shift from aluminum to copper interconnects at 130nm caused one of the most painful... » read more

Making Chip Packaging Simpler
By Ed Sperling and Mark LaPedus - 21 Mar, 2019 - Comments: 1

Packaging is emerging as one of the most critical elements in semiconductor design, but it's also proving difficult to master both technically and economically. The original role of packaging was simply to protect the chips inside, and there are still packages that do just that. But at advanced nodes, and with the integration of heterogeneous components built using different manufacturing pr... » read more

2.5D, 3D Power Integrity
By Ed Sperling - 14 Mar, 2019 - Comments: 0

Chris Ortiz, principal applications engineer at ANSYS, zeroes in on some common issues that are showing up in 2.5D and 3D packaging, which were not obvious in the initial implementations of these packaging technologies. This includes everything from how to build a power delivery network to minimize the coupling between chips to dealing with variability and power integrity and placement of diffe... » read more

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