tag: advanced packaging

Momentum Builds For Advanced Packaging
By Mark LaPedus - 17 Sep, 2020 - Comments: 0

The semiconductor industry is stepping up its efforts in advanced packaging, an approach that is becoming more widespread with new and complex chip designs. Foundries, OSATs and others are rolling out the next wave of advanced packaging technologies, such as 2.5D/3D, chiplets and fan-out, and they are developing more exotic packaging technologies that promise to improve performance, reduce p... » read more

OIP Ecosystem Forum 2020
By Paul McLellan - 10 Sep, 2020 - Comments: 0

Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual, the format was similar to the usual. Cliff Hou, Senior Vice President of Technology Development, opened the day with a summary of where everything is in the ecosystem around each of the new processes. There were then three keynotes by the leaders of the three big EDA companies. That was followed by more technical ... » read more

NanoResolution MRS Sensor: Fast, Precise 3D Inspection And Measurement for Advanced Semiconductor Packaging Applications
By CyberOptics - 08 Sep, 2020 - Comments: 0

The semiconductor packaging industry continues to advance, with new designs adding more layers, finer features and more I/O channels to achieve faster connections, higher bandwidth and lower power consumption. As packaging technologies have evolved, manufacturers have adapted old processes and adopted new processes to connect chips to each other and to the outside world. Often these new process... » read more

Interconnects Emerge As Key Concern For Performance
By Ed Sperling - 03 Sep, 2020 - Comments: 0

Interconnects are becoming increasingly challenging to design, implement and test as the amount of data skyrockets and the ability to move that data through denser arrays of compute elements and memories becomes more difficult. The idea of an interconnect is rather simple, but ask two people what constitutes an interconnect and you're likely to get very different answers. Interconnects are e... » read more

New Architectures, Much Faster Chips
By Ed Sperling and Ann Mutschler - 31 Aug, 2020 - Comments: 0

The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

Understanding Advanced Packaging Technologies And Their Impact On The Next Generation Of Electronics
By Sandy Wen - 28 Aug, 2020 - Comments: 2

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip to encompassing a growing number of schemes for interconnecting multiple types of chips. Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high device density in ... » read more

Moore’s Law Enters The 4th Dimension
By Ed Sperling - 21 Aug, 2020 - Comments: 5

The basic idea that more transistors are better hasn't changed in more than half a century. In fact, the overriding theme of a number of semiconductor conferences this month is that we will never have enough compute capability or storage capacity. In the past, when the number of transistors in a given area actually did double every 18 to 24 months, increasing density per square millimeter fo... » read more

Preparing For A Barrage Of Physical Effects
By Ann Mutschler - 13 Aug, 2020 - Comments: 0

Advancements in 3D transistors and packaging continue to enable better power and performance in a given footprint, but they also require more attention to physical effects stemming from both increased density and vertical stacking. Even in planar chips developed at 3nm, it will be more difficult to build both thin and thick oxide devices, which will have an impact on everything from power to... » read more

Power And Performance Optimization At 7/5/3nm
By Ed Sperling - 13 Aug, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Advanced Packaging, Heterogeneous Integration And Test
By FormFactor - 11 Aug, 2020 - Comments: 0

Major products rely on advanced packaging to reach the market; a groundswell of die-integration technologies are revolutionizing packaging, assembly, and test. At this exciting time in the industry, open engagement between customers and suppliers has never been more important for the test community. Click here to read more. » read more

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