tag: Advantest

5G Chips Add Test Challenges
By Bryon Moyer - 06 Jul, 2021 - Comments: 1

The advent of chips supporting millimeter-wave (mmWave) 5G signals is creating a new set of design and testing challenges. Effects that could be ignored at lower frequencies are now important. Performing high-volume test of RF chips will require much more from automated test equipment (ATE) than is required for chips operating below 6 GHz. “MmWave design is a pretty old thing,” said Y... » read more

Cleaning Up During IC Test
By Anne Meixner - 06 Jul, 2021 - Comments: 2

Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

Development Of High Voltage General-Purpose Pin-Electronics
By Advantest - 06 Jul, 2021 - Comments: 0

Currently, there is a demand in Automated Test Equipment (ATE) to test both high-speed/low-voltage amplitude devices manufactured in advanced processes and low-speed / high-voltage amplitude devices manufactured in legacy processes by a pin-electronics equipment. However, it is difficult to achieve both the operating speed over than 1Gbps and the wide I/O range over than 10Vpp, due to the trade... » read more

Driving Toward Predictive Analytics With Dynamic Parametric Test
By Alan Hart - 06 Jul, 2021 - Comments: 0

The foundation of parametric test within semiconductor manufacturing is its usefulness in determining that wafers have been fabricated properly. Foundries use parametric test results to help verify that wafers can be delivered to a customer. For IDMs, the test determines whether the wafers can be sent on for sorting. Usually inserted into the semiconductor manufacturing flow during wafer fabric... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 02 Jul, 2021 - Comments: 0

Chipmakers and OEMs More delays and product woes at Intel. “INTC disclosed that it is delaying the launch of its next-generation Xeon server processor Sapphire Rapids (10nm) from the end of this year to 1Q22 due to additional validation needed for the chip,” said John Vinh, an analyst at KeyBanc, in a research note. “Production is expected to begin in 1Q22, with the ramp expected to begi... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 18 Jun, 2021 - Comments: 0

Automotive U.S. electric truck manufacturer Lordstown Motors has an electric truck but after a large buyer fell through, it admitted it does not have any firm orders on its trucks, according to an AP story. The CEO and CFO resigned earlier this week. The electric car company Canoo announced its US manufacturing facility will be in Oklahoma. Cadence revealed its Tensilica FloatingPoint DSP (... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 11 Jun, 2021 - Comments: 0

Chipmakers SiFive has received a takeover offer from Intel, according to a report from Bloomberg. The asking price is more than $2 billion. ------------------------------------------------------------------ IBM has filed suit against GlobalFoundries (GF), alleging fraud and breach of contract committed by GF. IBM’s suit, filed in the Supreme Court of the state of New York, seeks relief... » read more

There’s More To Machine Learning Than CNNs
By Bryon Moyer - 09 Jun, 2021 - Comments: 1

Neural networks – and convolutional neural networks (CNNs) in particular – have received an abundance of attention over the last few years, but they're not the only useful machine-learning structures. There are numerous other ways for machines to learn how to solve problems, and there is room for alternative machine-learning structures. “Neural networks can do all this really comple... » read more

Reliability Costs Becoming Harder To Track
By Ed Sperling And Susan Rambo - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

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