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Inspecting, Testing, And Measuring SiC

Demand for solutions is booming, but the technology is just beginning to gain its footing.


Achieving the auto industry’s stringent zero defect goals is becoming a big challenge for makers of silicon carbide substrates, which are struggling to achieve sufficient yields and reliability as they migrate from 150mm to 200mm wafers and shift their focus away from pure silicon.

SiC is a combination of silicon and harder carbide materials, and it has emerged as a key technology for battery electric vehicles due to its wide bandgap. Silicon carbide works at higher power, higher temperatures, and higher switching frequencies than silicon. Those properties can be leveraged to increase the range of EV batteries and shorten the charging time.

“People want to charge their car in under 10 to 15 minutes, and that will continue to evolve,” said Sam Geha, CEO of Infineon Technologies’ Memory Solutions. “That will require silicon carbide and other technologies, and a lot more automation.”

There is no shortage of companies rushing to fill this void, as evidenced by recent investments. Last month, onsemi announced a deal to buy GT Advanced Technologies’ SiC technology for $415 million. Likewise, STMicroelectronics bought Norstel AB in 2019 for $137.5 million (total value; ST already owned 55%). In addition, Cree announced in 2019 that it would build a $1.2 billion 200mm SiC fab in Marcy, N.Y., with production scheduled to start next year.

Still, the supply chain still has some rough spots to iron out. This is partly due to reliability issues that are yet to be fully solved, and partly due to volume manufacturing ramp-up issues for any new material or changes in the size of wafers. A key challenge is to lower the defectivity, or dislocations, and for SiC substrates this is trickier than for standard silicon.

“The main challenges in producing SiC stem from the wafer level,” said Ahmed Ben Slimane, technology and market analyst for Compound Semiconductor & Emerging Substrates at Yole Développement. “SiC crystalline growth requires very high temperatures and a very slow growth rate, resulting in a low-yield substrate manufacturing process. Besides, the intrinsic properties of SiC, such as high hardness values, make it difficult to slice and polish, rendering the SiC wafer prone to various defects.”

As with all new processes, it takes time to understand the intricacies of what works best, what goes wrong, and how to either resolve or work around any issues. What’s different with SiC is that demand is exploding, largely because of the race to electrify vehicles, while the technology is still early in the ramp cycle.

“The patterning on silicon carbide today is relatively large,” said Jay Rathert, senior director of strategic collaborations at KLA. “The problems are in the substrate. But when we look at silicon carbide, and wide bandgap in general, it’s a little bit like the Wild West. Everybody’s trying to accelerate their learning and maturity as fast as they can. If we reach out into the ecosystem today and ask, ‘Hey, would you like a workshop on silicon carbide where we can tell you about the defect issues and the control methods and general trends,’ 8 out of 10 people are going to say yes.”

KLA and Lasertec sell inspection systems for SiC. These tools combine two technologies—surface defect inspection and photoluminescence metrology. Photoluminescence is a non-contact spectroscopy technique, which looks at the crystal structures of devices. Finding defects through inspection and other means is essential for improved reliability.

Eliminating defects
Actually reducing the defectivity rate has an economic benefit, too, and one way to tackle that is through well-controlled epitaxy.

“Today, major players have the know-how and experience to optimize their epitaxies to avoid critical defects propagating through the epilayer stack,” Yole’s Ben Slimane said. “At the process level, the gate oxide is one of the main challenges for SiC devices which can result in shorter lifetime devices. High-temperature burning tests are essential to optimize this step and avoid this problem. Besides, SiC is not CMOS-compatible, making it challenging to leverage Si technology processes as well as the infrastructure and requires investments to adapt existing fabs or build new ones.”

SiC is still evolving, and early defect detection is helping to improve the yield, he noted. Although trench structures remain more complicated to produce compared to planar structures, both devices have been implemented in commercial systems, and new generations are coming. “Testing and analysis equipment is vital to increase the yield,” said Ben Slimane. “Detecting defects and understanding their origins early in the process saves costs and improves the process.”

At the wafer level, high-throughput surface defect inspection helps to detect various types of defects, such as crystalline stacking faults, micropipes, pits, scratches, stains, and surface particles, according to Ben Slimane. “The transparency and the high reflectivity of SiC wafers make this step challenging. At the epitaxy level, high run-to-run reproducibility and better uniformity at large wafer sizes are mandatory. The ability to accurately and quickly detect and categorize defects using surface inspection and photoluminescence can reduce kill ratios. The gate oxide problem at the device level can be detected through the time-dependent dielectric breakdown (TDDB) inspection technique. Lower throughput, complexity, and original inspection tools can increase production cost, though they can also optimize the process and eventually increase yields. In addition, the industry is working on 200mm SiC. The transition to a larger wafer would require extra effort at the inspection and testing phase.”

Different materials have different levels of reflectivity when it comes to optical inspection, and the problem has become more complicated still when these various materials are used in different configurations and packages. Inspection tools have to keep pace with a variety of changes as new materials are introduced and used in both planar and complex heterogeneous packages.

“We have a sample of one of the more advanced packages right now in our lab, and they’re asking us to inspect it,” said Subodh Kulkarni, CEO of CyberOptics. “On one hand, you have this extremely shiny 20µm copper bump on a pillar and you have this perfect hemisphere on top. And we are looking at optical technology. So literally, you get one pixel that we can look at in the camera, and we are trying to infer the height of that bump with that one pixel. That’s one extreme where it’s perfectly reflective everything. But then the whole thing is sitting on a very diffused substrate, and there’s no reflectivity whatsoever. So we’re dealing with dealing with these issues. How do you design a projector dynamic range where you have such low k highly diffusive substrate, versus a highly shiny, perfectly curved copper mirror. It’s a challenge for the optical side to design the dynamic range of our projection scheme so the detectors don’t get oversaturated or don’t see any signal at all. It’s becoming much more of an issue in the substrate world than in the wafer world.”

Other techniques like X-ray diffraction (XRD) also are being deployed for SiC. XRD is used to characterize crystalline materials. Deployed in the industry for years, XRD first made inroads in the semiconductor industry for logic. It was, and still is, used to characterize silicon germanium (SiGe) materials in devices. 

Over time, XRD has moved to other areas. “It has been added to the compound side, like for gallium-nitride. We have a big market for high-performance LEDs and III-V materials,” said Paul Ryan, vice president and general manager of the X-ray Business Unit at Bruker. “The next big up and comer is silicon carbide, looking at the quality on that either with straight diffraction or diffraction imaging.”

In addition, tools that locate and map defects on SiC wafers are commercially available and are typically based on UV irradiation of the wafer. This mapping, with defect type and impact criteria, determines the wafer’s usable area.

The goal is to produce SiC wafers with very low performance-degrading defects. “Substrate manufacturers are continuously improving material quality,” said Victor Veliadis, executive director and CTO for the PowerAmerica Manufacturing USA Institute, which was formed by the U.S. Dept. of Energy to accelerate adoption of SiC and GaN power electronics. “At the epitaxial layer deposition level, the goal is to restrict substrate defects from propagating into the epitaxy, or to allow for substrate ‘performance-degrading’ defects to propagate as benign defects.”

This is in addition to ensuring doping and thickness uniform epitaxy. “SiC substrate growth is more labor-intensive and complex than that of silicon, and today represents an astounding 50% to 70% of the SiC device cost,” Veliadis said. “Unlike silicon, SiC does not melt at practical temperatures, but rather sublimes at about the 2,500°C growth temperature. A high-material quality SiC large seed is required and there is limited crystal expansion.”

In addition, sawing and polishing are “difficult” due to the hardness of the SiC material. The result is very expensive SiC wafers, and ultimately higher device costs, Veliadis added. “A key part of the vertical integration occurring in today’s SiC industry is securing internal substrate and epitaxy wafer capabilities to eliminate purchasing profit margins. It should be noted that opportunities for disruptive SiC substrate growth, boule slicing, sawing/polishing, etc., have a high return and are sought by several companies.”

Manufacturing high-quality and reliable silicon-carbide devices requires an interplay of several disciplines, including process capability and experience. Robert Hermann, Infineon’s senior director and head of product marketing for high voltage conversion, noted his company introduced the trench-MOSFET structure years ago. “One benefit is a strongly improved RDS(ON) x A, meaning higher volume and also better yield. The smaller the dies are, the less relevant the non-perfect raw wafer gets. For this device structure, especially the gate-oxide structure, process mainly influences reliability.”

Fig. 1: Planar-gate MOSFET (left) and trench MOSFET (right). Source: Infineon

In terms of yield, SiC today is roughly where silicon was 30 years ago, said Bret Zahn, vice president and general manager of onsemi’s Electric Vehicle Traction Power Module Business Unit. “The primary yield detractor originates from the initial step of the SiC crystal substrate growth itself. The fundamental infusion of the carbide atoms into silicon to form SiC produces defect density, and this is where the biggest technology challenge lies. Substrate fabrication is a slow and expensive process. Given increasing demand, stronger investment in research and development and production is required to improve the fabrication process.”

That process is extremely complex. “Semiconductor fabrication encompasses a few hundred process steps to pattern a few million transistor cells into a single usable chip,” Zahn said. “During fabrication, an inherent parts-per-million (PPM) level failure rate is commonly observed, and this is termed defect density. These defective chips are sorted out and rejected during the wafer probing operations. Defect density reduction is partly inherent to the technology design itself and the process of fabricating the semiconductor. Both areas require in-depth engineering expertise.”

For automotive applications, this adds a whole new level of concern. Carmakers are demanding that chips function to spec for as long as 18 years. “Quality requirements will come into play at every aspect of the test and product lifecycle,” said Keith Schaub, vice president of technology and strategy at Advantest America. “And that will drive up cost. But at the same time, engineers are really good at taking on challenges like that and coming up with lower-cost solutions, which is one of the reasons the auto industry has been so successful.”

Common testing today include statistical analysis of electrical parameters and pattern analysis of wafer maps. “In some cases, further physical analysis such as chemical delayering and focused ion beam analysis (FIB) may be required,” Zahn said. “The goal is to establish a connection between those defects that have occurred and what could have caused them during fabrication. Once this is established, the root cause can be addressed.”

High magnification inline optical analysis to detect defects is employed, as well, in order to detect failure modes earlier in the fabrication process, Zahn added. Substrate production requires different fabrication tools and steps than producing end devices, with dedicated optimization steps. “Vertically integrated SiC suppliers have proprietary wafer and components level testing techniques to intercept and eventually minimize defect density, increase yield at component level, provide customers with quality and reliable final material, and achieve robustness comparable and inherently superior to silicon due to the characteristics of the technology.”

Metrology adds another challenge. “We have a very good position in metrology of GaN and SiC,” said Paul Knutrud, director of marketing, Optical Products, Onto Innovation. “Both of these substrates are challenging for both metrology and lithography due to their transparency at visible optical wavelengths.”

Knutrud noted that both GaN and SiC devices appear to be taking off. “GaN is replacing GaAs and silicon in a number of power applications such as military, cell towers, health care and consumer electronics. The high power and high switching speeds are the major advantages of GaN. SiC is ideal for electric vehicle power conversion chips due to the high breakdown field strength, thermal conductivity and efficiency.”

Moving to 200mm
The transition of SiC to 200mm wafer technologies adds other issues, and it will take time to work out all the bugs.

“The industry is indeed eagerly waiting for 200mm wafers to become commercially available, preferably from several vendors,” Veliadis said. “200mm SiC wafers were demonstrated in 2015, and a seven-years or so period historically passes before they are available as products. Due to the large fab/foundry overheads, and assuming the tools are in place, the cost of processing a wafer is unrelated to its size. So processing a 200mm wafer will produce about 1.7 times more devices than a 150mm wafer at the same processing cost. Of course, a 200mm wafer will be more expensive than a 150mm wafer, and same cost per cm² is a good assumption.”

Veliadis notes there are two issues to overcome for producing 200mm wafers. “Defect density, or defects per cm2 of area, is the same or lower for 200mm vs. 150mm wafers. Second, cost of material per cm2 is the same or lower for 200mm vs. 150mm wafers. And, of course, wafer planarity should not be worse in the 200 mm wafers. So the same or better material quality for 200mm at the same per cm2 cost as 150 mm are desirable. Fabrication processes for 200mm wafers will need to be qualified, and qualifications lots will need to be run. That is part of the pain of moving to a higher-area wafer. But the larger number of devices fabricated at same fabrication cost — not the overall cost, as the 200mm wafer is more expensive than a 150mm wafer — is a strong incentive, as is the need to meet the higher EV demand for SiC devices.”

Many silicon fabs are starting to process SiC wafers, as well, and given the plethora of 200mm Si fabs with fully depreciated tools, there are a lot of large 200mm fabs/foundries waiting on the sidelines to enter SiC production when 200 mm wafers become available.

“These are companies that migrated to 200mm silicon wafers a while back and do not want to retool to fabricate at the 150mm wafer size that is currently commercially available for SiC,” Veliadis noted. “So when 200mm wafers become available, we will see many 200mm fabs start producing SiC devices. For EV power, 200mm wafers will help meet the rising demand. As far as testing and analysis, the 200mm tools will handle the job with some modification specific to testing SiC similar to the 150mm case.”

Still, this all takes time. “It is true that GaN- and silicon-based devices are well established in power and RF applications,” said David Haynes, managing director of strategic marketing for the customer support business group at Lam Research. “But this is largely on wafers that are six inches or smaller in the case of many GaN-based devices on substrates such as sapphire and SiC. Today there is a strong shift to 200mm wafer processing in order to increase compatibility of these technologies with mainstream semiconductor processing, and to improve the economics of the technology for more advanced or higher volume applications.”

How long this takes remains to be seen, but it certainly will happen within the next few years. “SiC is migrating to 200mm, with production set to ramp in the next two to three years as 200mm wafer cost and availability improves,” Haynes said. “In particular, Lam is focusing its efforts on 200mm SiC trench MOSFET applications.”

For GaN, it is the improved performance of GaN on silicon technologies on 200mm, he said. In the future, even 300mm is likely. “The processing of 200mm GaN on silicon power and RF devices really opens up the possibilities for CMOS integration and compatibility with CMOS foundry processing. At Lam, we have developed a range of ultra-low-damage etch and deposition processes compatible with 200mm and 300mm GaN on silicon production, as well as advanced single wafer clean processes to support CMOS foundry compatibility.”

Silicon carbide is in high demand for a variety of applications, particularly in the automotive sector, but the processes to identify and control defects still need some work. Some of this is due to a shift to larger wafer sizes, and by way of comparison, the ramp from 200mm to 300mm for bulk silicon was difficult. This is compounded by the fact that SiC is being used increasingly in safety-critical applications, where defects can result in injury or death, and in automotive applications where there is extreme pressure to reduce costs by improving yield.

All of this will take time, but the market outlook is strong. So from a business standpoint, there is strong incentive to solve these issues quickly, and no shortage of companies looking to do that.

— Ed Sperling and Mark LaPedus contributed to this report.

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