Optimization Driving Changes In Microarchitectures


The semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of AI, and the need for differentiation and customization in leading-edge applications. In the past, much of this would have been accomplished by moving to the next process node. But with the benefits from scaling diminishing at each new node, the focus is s... » read more

Microelectronics And The AI Revolution


It is no secret that artificial intelligence and machine learning (AI/ML) are critical drivers for growth in electronics, and particularly, for semiconductors. The recent AI Hardware Summit showcased trends in AI/ML, both in enabling and using it in various application domains, including EDA. As part of the summit, Imec had organized a panel on “Advanced Microelectronics Technologies Driving ... » read more

Building Complex Chips That Last Longer


Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Using ML In EDA


Machine learning is becoming essential for designing chips due to the growing volume of data stemming from increasing density and complexity. Nick Ni, director of product marketing for AI at Xilinx, examines why machine learning is gaining traction at advanced nodes, where it’s being used today and how it will be used in the future, how quality of results compare with and without ML, and what... » read more

Deploying Artificial Intelligence At The Edge


By Pushkar Apte and Tom Salmon Rapid advances in artificial intelligence (AI) have made this technology important for many industries, including finance, energy, healthcare, and microelectronics. AI is driving a multi-trillion-dollar global market while helping to solve some tough societal problems such as tracking the current pandemic and predicting the severity of climate-driven events lik... » read more

Tradeoffs Between Edge Vs. Cloud


Increasing amounts of processing are being done on the edge, but how the balance will change between what's computed in the cloud versus the edge remains unclear. The answer may depend as much on the value of data and other commercial reasons as on technical limitations. The pendulum has been swinging between doing all processing in the cloud to doing increasing amounts of processing at the ... » read more

On the Road To Higher Memory Bandwidth


In the decade since HBM was first announced, we’ve seen two-and-a-half generations of the standard come to market. HBM’s “wide and slow” architecture debuted first at a data rate of 1 gigabit per second (Gbps) running over a 1024-bit wide interface. The product of that data rate and that interface width provided a bandwidth of 128 gigabytes per second (GB/s). In 2016, HBM2 doubled the s... » read more

How To Maximize Your Competitiveness In The Semiconductor Industry Using Advanced DFT


Embarking on advanced SoCs without a smart design-for-test (DFT) strategy can be harmful to your bottom line. Being competitive in today’s semiconductor market means adopting integrated, scalable, and flexible solutions to cut DFT implementation time, test costs, and time-to-market. Tessent DFT technologies, developed in partnership with industry leaders, provide the most advanced DFT and yie... » read more

Fabs Drive Deeper Into Machine Learning


Advanced machine learning is beginning to make inroads into yield enhancement methodology as fabs and equipment makers seek to identify defectivity patterns in wafer images with greater accuracy and speed. Each month a wafer fabrication factory produces tens of millions of wafer-level images from inspection, metrology, and test. Engineers must analyze that data to improve yield and to reject... » read more

How Dynamic Hardware Efficiently Solves The Neural Network Complexity Problem


Given the high computational requirements of neural network models, efficient execution is paramount. When performed trillions of times per second even the tiniest inefficiencies are multiplied into large inefficiencies at the chip and system level. Because AI models continue to expand in complexity and size as they are asked to become more human-like in their (artificial) intelligence, it is c... » read more

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