To (B)atch Or Not To (B)atch?


When evaluating benchmark results for AI/ML processing solutions, it is very helpful to remember Shakespeare’s Hamlet, and the famous line: “To be, or not to be.” Except in this case the “B” stands for Batched. Batch size matters There are two different ways in which a machine learning inference workload can be used in a system. A particular ML graph can be used one time, preced... » read more

AI’s Ability To Deliver Breakthroughs Across Semiconductor Design And Manufacturing


AI holds great promise for our industry. It will help close the divide between design, manufacturing and test that is required to effectively produce today’s most advanced hybrid devices. One way to look at the potential impact of AI in the semiconductor industry is to realize that it is more and more driven by software engineering. When designing a chip, it’s essentially like writing... » read more

Yield Management Embraces Expanding Role


Competitive pressures, shrinking time-to-market windows, and increased customization are collectively changing the dynamics and demands for yield management systems, shifting left from the fab to the design flow and right to assembly, packaging, and in-field analysis. The basic role of yield management systems is still expediting new product introductions, reducing scrap, and delivering grea... » read more

Scaling Performance In AI Systems


Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks about where the bottlenecks are, how to ... » read more

Why 40G UCIe IP?


AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more

Reducing SoC Power With NoCs And Caches


Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

AI’s Power To Transform Semiconductor Design And Manufacturing


Artificial intelligence and machine learning (AI/ML) have immense power to transform semiconductor design and manufacturing for a variety of broad and far-ranging applications. Just consider the volume of data generated by design and manufacturing each year. With increasingly complex products, machines, processes and supply chains, the overall amount of data associated with semiconductor making... » read more

Chip Industry Week In Review


Europe's top court ruled in Intel's favor, voiding a $1.1 billion fine imposed by the European Union and dismissing charges of anti-competitive behavior. IBM released yield benchmarks for high-NA EUV, which serve as proof points that the newest advanced litho equipment will enable scaling beyond the 2nm process node. Also on the lithography front, Nikon is developing a maskless digital litho... » read more

Reactionary Or Anticipatory?


The EDA industry is located at an interesting place, where anticipation and reaction come together. Too much of either one is wasteful, but too little leaves the industry having to deal with unwanted problems. We see this happening in several areas today, and the balance is changing for several reasons. We normally expect universities to be 100% anticipatory. There is no point in them worki... » read more

LLMs Show Promise In Secure IC Design


The introduction of large language models into the EDA flow could significantly reduce the time, effort, and cost of designing secure chips and systems, but they also could open the door to more sophisticated attacks. It's still early days for the use of LLMs in chip and system design. The technology is just beginning to be implemented, and there are numerous technical challenges that must b... » read more

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