Week In Review: Manufacturing, Test

By Mark LaPedus - 04 Mar, 2022 - Comments: 0

Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

AiP/AiM Design For mmWave Applications — Advanced RF Front-End Design Flows From Concept To Signoff

By Cadence - 08 Jul, 2021 - Comments: 0

System requirements for broad bandwidth, millimeter-wave (mmWave) spectrum, phased arrays, and integrated antennas and front-ends are evolving. The challenge for engineers will be achieving the cost, size, and performance requirements that will make these products commercially viable. All these factors align to drive next-generation component integration, which includes embedding the antenna wi... » read more

Attaching Fibers To Photonic Chips

By Paul McLellan - 10 Dec, 2020 - Comments: 0

Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts: Photonic Integration—From Switching to Computing How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs The third day was all about how to connect the incoming and outgoing fibers to the photonics chips. I will cov... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 04 Dec, 2020 - Comments: 0

Packaging and EMS ASE is expanding its efforts in the electronic manufacturing services (EMS) business. Universal Scientific Industrial (USI), a subsidiary of ASE, has completed the acquisition of Asteelflash Group through the acquisition of its parent company, Financière. USI provides electronic design and manufacturing services. It also provides system-in-package (SiP) modules. Asteelfla... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: AIM

Week In Review: Manufacturing, Test

AiP/AiM Design For mmWave Applications — Advanced RF Front-End Design Flows From Concept To Signoff

Attaching Fibers To Photonic Chips

Week In Review: Manufacturing, Test