tag: Aldec

Blog Review: Mar. 21
By Jesse Allen - 21 Mar, 2018 - Comments: 0

Mentor's Colin Walls shares five more quick tips for embedded software programming, including t real time systems, programming philosophy, and C++ operator overloading. Cadence's Paul McLellan digs into recently released semiconductor company ratings, the role of memory in shaking up the list, and China's plans for more 3D NAND and DRAM fabs. Synopsys' Taylor Armerding examines the latest... » read more

Blog Review: Mar. 7
By Jesse Allen - 07 Mar, 2018 - Comments: 0

Synopsys' Amit Paunikar and Shaily Khare take a look at new features in LPDDR5, from improved data bandwidth and Deep Sleep Mode to WCK clock. Cadence's Paul McLellan dives into forward error correction, a technique for automatically correcting errors in transmitted network data, with a look at why it's important and how it works. In his latest embedded software video, Mentor's Colin Wall... » read more

Anatomy Of An Autonomous Vehicle Crash
By Ann Mutschler - 01 Mar, 2018 - Comments: 0

The rollout of autonomous vehicles will have far-reaching impacts on technology, business and social interactions, but it also will set in motion a whole new side of technology development and new legal frameworks to prove what went wrong when these vehicles are involved in an accident. This isn't just something to plan for down the road. The California Department of Motor Vehicles this week... » read more

The Week In Review: Design
By Jesse Allen - 23 Feb, 2018 - Comments: 0

Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

Debugging Debug
By Brian Bailey - 22 Feb, 2018 - Comments: 2

There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Inside UVM, Take Two
By Vatsal Choksi - 22 Feb, 2018 - Comments: 0

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. So, let’s look at the main concepts and follow the communication mechanism they use for... » read more

Partitioning Challenges In Multi-FPGA Prototyping
By Aldec - 21 Feb, 2018 - Comments: 0

Multi-FPGA prototyping of ASIC & SoC designs enables the highest clock rates among emulation techniques. However, design setup for prototyping is much more complicated and challenging. In this White Paper we uncover the common challenges of partitioning design to multiple FPGAs and provide solutions that will improve your prototype quality and shorten time spent on design setup. To read ... » read more

The Week In Review: Design
By Jesse Allen - 09 Feb, 2018 - Comments: 0

M&A Synopsys acquired PhoeniX Software, expanding its photonic integrated circuit design range. Founded in 2003 and based in the Netherlands, PheoniX adds photonic aware physical layout capabilities, enabled by support for foundry-specific PDKs, along with a full photonic chip design package. Terms of the deal were not disclosed. Siemens PLM Software will acquire Sarokal Test Systems, w... » read more

Blog Review: Jan. 31
By Jesse Allen - 31 Jan, 2018 - Comments: 0

Cadence's Paul McLellan looks back at where TSMC was 30 years ago and the founding philosophy that made the foundry and fabless model work. In a video, Mentor's Colin Walls considers how to make the simplest possible multitasking scheduler with a one line RTOS. Synopsys' Sandeep Taneja checks out the technology behind airbags in cars and the role of the Motorola Serial Peripheral Interfac... » read more

Achieving RTL-To-Netlist Equivalence
By Aldec - 30 Jan, 2018 - Comments: 0

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, there is a need to ensure flawless transformation of RTL code to the technology-dependent netlist. This in turns sets the requirements for the “design-for-implementation” coding, where designers ... » read more

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