tag: Aldec

Why I See C In SCE-MI
By Jacek Majkowski - 24 Mar, 2016 - Comments: 0

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

Q&A With FAA DO-254
By Aldec - 23 Mar, 2016 - Comments: 0

Aldec together with FAA DER Randall Fulton conducted a webinar to provide clarifications on some of the most commonly misunderstood objectives and aspects of DO-254. The following is the list of questions that were submitted to Aldec for the webinar. All questions are related to applying DO-254 to FPGAs and PLDs. The answers from Randall Fulton are provided correspondingly. To read more, c... » read more

The Week In Review: Design/IoT
By Jesse Allen - 18 Mar, 2016 - Comments: 0

Tools Aldec updated its emulation and simulation acceleration software package for high speed prototyping boards, adding a SCE-MI Pipes-based flow for streaming large amounts of data, and a 30% speed increase for all emulation modes. Plus, Aldec's mixed-language FPGA design and simulation platform now includes a complete coverage analysis package for FPGA and ASIC designers with the addition... » read more

The Week In Review: Design/IoT
By Jesse Allen - 11 Mar, 2016 - Comments: 0

Legal A federal court jury favored Synopsys in a 2013 lawsuit alleging that ATopTech violated copyright by copying elements of the command set for Synopsys' PrimeTime static timing analysis product. Synopsys was awarded $30.4 million in damages. ATopTech plans to contest the verdict, stating that other issues in the case remain to be decided. Tools Aldec unveiled the latest version of ... » read more

The Week In Review: Design/IoT
By Jesse Allen - 26 Feb, 2016 - Comments: 0

Tools Synopsys incorporated automated analog and mixed-signal debug capabilities into its Verdi SoC debug platform, which now provides comprehensive hierarchical and schematic views of both the analog and digital portions of designs and automated tracing across analog and digital blocks. Mentor announced three applications for the Veloce emulation platform focused on overcoming unpredicta... » read more

Racing To Design Chips Faster
By Ed Sperling - 25 Feb, 2016 - Comments: 6

A shift is underway to develop chips for more narrowly defined market segments, and in much smaller production runs. Rather than focusing on shrinking features and reducing cost per transistor by the billions of units, the emphasis behind this shift is less about scale and much more about optimization for specific markets and delivering those solutions more quickly. As automotive, consumer e... » read more

UVM: It’s Organized And Systematic
By Henry Chan - 25 Feb, 2016 - Comments: 0

One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamental... » read more

Managing Validation And Verification Abstract Activities For DO-254
By Aldec - 24 Feb, 2016 - Comments: 0

This paper provides an overview of the Validation and Verification (V & V) process and its associated activities as described in RTCA/DO-254. With the growing size and complexity of today’s FPGAs, managing V & V activities is becoming difficult and time-consuming. This paper presents a list of recommended features, methodologies and capabilities that must be supported by a tool to manage V & ... » read more

Debug Becomes A Bigger Problem
By Brian Bailey - 11 Feb, 2016 - Comments: 3

The EDA industry has invested enormous amounts of time and energy on the verification process, including new languages, new tools, new class libraries, new methodologies. But the one part of the cycle that defines that type of automation is debug. Development teams are spending half of their time in the debug process and the problem is growing. Part of the reason is that design and debug are... » read more

The Week In Review: Design/IoT
By Jesse Allen - 05 Feb, 2016 - Comments: 0

Events DAC is now accepting nominations for the Marie R. Pistilli Women in EDA Achievement Award, which recognizes individuals who have visibly helped to advance the profile of women in the EDA industry. Nominations must be received by March 3rd. Tools Cadence unveiled its new Modus Test Solution, which the company says enables design engineers to achieve an up to 3X reduction in test ... » read more

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