The Week In Review: Manufacturing

By Mark LaPedus - 20 Mar, 2015 - Comments: 0

For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above work for Altera. Now, Altera will soon select a foundry partner for 10nm. “Altera will make a decision on which foundry partner it will choose for 10nm finFET at the end of 1Q15, noting it will decide between Intel and TSMC,” said John Vin... » read more

Week 41: The Rise Of Security At DAC

By Anne Cirkel - 20 Mar, 2015 - Comments: 0

All potential attendees interested in security topics should know one thing—the Wednesday keynote on hacking automobiles, while sure to be compelling, will only scratch the surface of security-related content at DAC. Another presenter will talk about how increasing demand for “connected life on the go” and “Internet-enabled everything” opens up a wide variety of security issues for Io... » read more

Architecting For Optimal Interface IP Integration

By Ann Mutschler - 10 Mar, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss the design and integration of complex interface [getkc id="43" comment="IP"] with Ty Garibay, VP of engineering at Altera; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Saman Sadr, director of analog design at Semtech; and Nav... » read more

Defining Functional Accuracy

By Jon McDonald - 26 Feb, 2015 - Comments: 0

I have been heavily involved in a project that recently completed. It involved creating virtual platforms (VPs) for a number of Altera’s FPGA SoCs. If you’re interested in more information, an announcement on the VP availability went out last week. Some of the modeled platforms existed and some were in various stages of development. The goal of the project was to deliver functionally acc... » read more

The Week In Review: Design/IoT

By Jesse Allen - 20 Feb, 2015 - Comments: 0

Deals Arteris teamed up with Yogitech to integrate the two companies' products. They're planning a set of ISO 26262 deliverables for a series of SoC reference designs and a functional safety assessment of the Arteris FlexNoC interconnect IP. ARM and Green Hills Software collaborated on an optimized compiler for the Cortex-R5 processor. The compiler achieved a score of 1.01EEMBC Automarks/... » read more

The Week In Review: Design/IoT

By Ed Sperling - 30 Jan, 2015 - Comments: 0

Mergers/Acquisitions Lattice Semiconductor agreed to pay $600 million for Silicon Image, which makes connectivity solutions for high-definition content for mobile and consumer electronics. Lattice already makes programmable connectivity solutions, so the combined IP portfolio is expected to strengthen its position in wired and wireless markets. Tools Cadence expanded the tool portfolio it ... » read more

Architecting For Optimal Interface IP Integration

By Ann Mutschler - 04 Dec, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the design and integration of complex interface IP with Ty Garibay, VP of engineering at Altera; Brian Daellenbach, president of Northwest Logic; Frank Ferro, senior director of product management for memory and interface IP at Rambus; Saman Sadr, director of analog design at Semtech; and Navraj Nandra, senior director of marketing for analog/mixed ... » read more

Hybrid Memory Cube – Ready For Prime Time

By Manohar Ayyagiri - 20 Nov, 2014 - Comments: 0

With the release this week of Hybrid Memory Cube (HMC) 2.0, designers can get their hands on mature, standards-based IP that can be used to significantly scale the performance of servers and data centers. HMC offers bandwidths up to 320 GB/s – 12X that of standard memory solutions like DDR4 – while consuming significantly less power. These benefits are too significant to ignore for ASIC, So... » read more

Design Rules Explode At New Nodes

By Ed Sperling - 17 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down changing design rules with Sergey Shumarayev, senior director of custom IP design at Altera; Luigi Capodieci, R&D fellow at [getentity id="22819" comment="GlobalFoundries"]; Michael White, director of product marketing for Calibre Physical Verification at [getentity id="22017" e_name="Mentor Graphics"], and Coby Zelnik, CEO of [getentity id="22478" e_name=... » read more

Are Models Holding Back New Methodologies?

By Brian Bailey - 11 Nov, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="101" kc_name="modeling"] at abstractions above [getkc id="49" kc_name="RTL"], a factor which has delayed adoption of [getkc id="104" kn_name="virtual prototypes"] and the proliferation of system-level design and hardware/software codesign. Taking part in the discussion were Frank Schirrmeister, group director... » read more

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tag: Altera

The Week In Review: Manufacturing

Week 41: The Rise Of Security At DAC

Architecting For Optimal Interface IP Integration

Defining Functional Accuracy

The Week In Review: Design/IoT

The Week In Review: Design/IoT

Architecting For Optimal Interface IP Integration

Hybrid Memory Cube – Ready For Prime Time

Design Rules Explode At New Nodes

Are Models Holding Back New Methodologies?

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