tag: AMD

Power Impact At The Physical Layer Causes Downstream Effects
By Ann Mutschler - 09 Jul, 2020 - Comments: 0

Data movement is rapidly emerging as one of the top design challenges, and it is being complicated by new chip architectures and physical effects caused by increasing density at advanced nodes and in multi-chip systems. Until the introduction of the latest revs of high-bandwidth memory, as well as GDDR6, memory was considered the next big bottleneck. But other compute bottlenecks have been e... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 26 Jun, 2020 - Comments: 0

Fast Arm-based supercomputer Japan has taken the lead in the supercomputer race, jumping ahead of the U.S. But China continues to make its presence felt in the arena. Fugaku, an ARM-based supercomputer jointly developed by Japan’s Riken and Fujitsu, is now ranked the world’s fastest supercomputer in the 55th TOP500 list. Fugaku turned in a high performance Linpack (HPL) result of 415.5... » read more

Over-Design, Under-Design Impacts Verification
By Ann Mutschler - 25 Jun, 2020 - Comments: 0

Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

Spreading Out The Cost At 3nm
By Ed Sperling - 18 Jun, 2020 - Comments: 5

The current model for semiconductor scaling doesn't add up. While it's possible that markets will consolidate around a few basic designs, the likelihood is that no single SoC will sell in enough volume to compensate for the increased cost of design, equipment, mask sets and significantly more testing and inspection. In fact, even with slew of derivative chips, it may not be enough to tip the ec... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 12 Jun, 2020 - Comments: 0

Edge, cloud, data center Programmable logic company Efinix used Cadence’s Digital Full Flow to finish Efinix’s Trion FPGA family for edge computing, AI/ML and vision processing applications, according to a press release. Last week Efinix also announced three software defined SoCs based on the RISC-V core. The SoCs are optimized to the Trion FPGAs. AI, machine learning Amazon will tempo... » read more

Fundamental Changes In Economics Of Chip Security
By Ed Sperling - 10 Jun, 2020 - Comments: 0

Protecting chips from cyberattacks is becoming more difficult, more expensive and much more resource-intensive, but it also is becoming increasingly necessary as some of those chips end up in mission-critical servers and in safety-critical applications such as automotive. Security has been on the semiconductor industry's radar for at least the past several years, despite spotty progress and ... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 05 Jun, 2020 - Comments: 0

Edge, cloud, data center Synopsys launched its USB4 IP and tools, already with a successful tapeout of a USB4 PHY test chip on 5nm advanced FinFET process. The Designware USB4 IP’s throughput is up to 20 or 40 Gbps, which Synopsys says is the bandwidth needed for high-performance edge AI, storage, PC, and tablet SoC designs. Also, Samsung Foundry certified Synopsys’ Design Compiler NXT for ... » read more

Designing The Next Big Things
By Ed Sperling - 05 Jun, 2020 - Comments: 0

The edge is a humongous opportunity for the semiconductor industry. The problem, despite its name, is that it's not a single thing. It will be comprised of thousands of different chips and systems, and very few will be sold in large volumes. The edge is the culmination of decades of improvement in power and performance, coupled with the architectural creativity that has exploded since the bene... » read more

The Good And Bad Of Chiplets
By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

‘More Than Moore’ Reality Check
By Ann Mutschler - 14 May, 2020 - Comments: 1

The semiconductor industry is embracing multi-die packages as feature scaling hits the limits of physics, but how to get there with the least amount of pain and at the lowest cost is a work in progress. Gaps remain in tooling and methodologies, interconnect standards are still being developed, and there are so many implementations of packaging that the number of choices is often overwhelming. ... » read more

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