tag: Amkor

Current And Future Packaging Trends
By Mark LaPedus - 19 Aug, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss IC packaging technology trends and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Thomas Uhrmann, directo... » read more

Empowering RF Front End Cellular Innovations With DSMBGA
By Curtis Zwenger - 19 Aug, 2021 - Comments: 0

With the introduction of 5G, cellular frequency bands have increased considerably, requiring innovative solutions for the packaging of RF front-end modules for smartphones and other 5G-enabled devices. Double-sided, molded ball grid array (DSMBGA) is a prime example of such solutions. “With our DSMBGA platform, we’ve established a preferred advanced packaging solution for this domain,”... » read more

Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS
By Amkor - 18 Aug, 2021 - Comments: 0

Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging [1]. Wafer-level fanou... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 13 Aug, 2021 - Comments: 0

Chipmakers and OEMs Samsung has announced its latest foldable smartphones--the Galaxy Z Fold3 5G and Galaxy Z Flip3 5G. The systems are based on Samsung’s 5nm application processor. One system is the company’s most affordable foldable phone. The Galaxy Z Fold3 is $1,799.99, while the Galaxy Z Flip3 is $999.99. Samsung also announced two smartwatches—the Galaxy Watch4 and Galaxy Watch4... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 30 Jul, 2021 - Comments: 0

Chipmakers Intel has outlined its new process technology roadmap with plans to regain the leadership position in the market. As part of the move, Intel has changed the way it designates the nodes, revealed its new gate-all-around (GAA) transistor, and disclosed a customer for the GAA technology--Qualcomm. And not to be outdone, Intel has broadened its packaging portfolio. Intel is changing ... » read more

Piecing Together Chiplets
By Mark LaPedus - 22 Jul, 2021 - Comments: 3

Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Will An Adhesion Promoter Prevent Delamination In Power Semiconductor Packages?
By Amkor - 21 Jul, 2021 - Comments: 0

Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid electric vehicles (HEV) in the automotive market, demands on (and for) power packages have been growing. Packages for automotive applications must pass extensive testing for safety, therefore, packaging reliability is essential. As more semiconductor pack... » read more

Cleaning Up During IC Test
By Anne Meixner - 06 Jul, 2021 - Comments: 2

Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging
By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

Fan-Out Packaging Options Grow
By Mark LaPedus - 17 Jun, 2021 - Comments: 0

Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge. Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and sma... » read more

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