tag: Amkor

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 28 Oct, 2022 - Comments: 0

This week saw more fallout from U.S. export controls: SK hynix may consider selling its memory chip production facilities in China if recently imposed controls make it too difficult to continue operations there, according to Nikkei Asia. "As a contingency plan, we are considering selling the fab, selling the equipment or transferring the equipment to South Korea," said Kevin Noh, SK hynix ... » read more

SiPs: The Best Things in Small Packages
By Laura Peters - 20 Oct, 2022 - Comments: 0

System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

Production Testing Of Discrete Power Products
By Vineet Pancholi - 20 Oct, 2022 - Comments: 0

By Vineet Pancholi and Dennis Dinawanao Metal Oxide Silicon Field Effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), Bipolar Junction Transistors (BJTs), diodes, and application specific multi-transistor packaged modules are some of the more popular discrete products. Switches control the flow of current within a circuit. MOSFETs are a building block of most electronic... » read more

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
By Karen Heyman - 11 Oct, 2022 - Comments: 1

Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Improving Redistribution Layers for Fan-out Packages And SiPs
By Laura Peters - 15 Sep, 2022 - Comments: 2

Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

Thermal Simulation Of DSMBGA And Coupled Thermal-Mechanical Simulation Of Large Body HDFO
By Nathan Whitchurch - 15 Sep, 2022 - Comments: 0

Electronic packaging has continued to become more complex with higher device count, higher power densities and Heterogeneous Integration (HI) becoming more common. In the mobile space, systems that were once separate components on a printed circuit board (PCB) have now been relocated along with all their associated passive devices and interconnects into single System in Package (SiP) style suba... » read more

Week In Review: Manufacturing, Test
By Karen Heyman - 09 Sep, 2022 - Comments: 0

Some funding details are now available for the CHIPS Act in the U.S. The Biden Administration plans to spend the money in the following ways: $28 billion to establish domestic production of leading-edge logic and memory chips through grants, subsidized loans or loan guarantees; $10 billion to increase production of current-generation semiconductors and chips, and $11 billion for rese... » read more

Fan-Out Packaging Gets Competitive
By Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Heterogeneous IC Packaging: Optimizing Performance And Cost
By Mike Kelly - 18 Aug, 2022 - Comments: 0

Leading integrated circuit (IC) foundries are already shipping 7-nm and 5-nm wafers and 3-nm product qualifications are ongoing. Wafer costs continue to soar as high transistor density requires ever more expensive processes to fabricate them. Even if defect densities can remain relatively flat as new nodes emerge, the cost per unit area of silicon increases nonlinearly. These economics have pla... » read more

Making The Most Of Data Lakes
By Anne Meixner - 09 Aug, 2022 - Comments: 0

Having all the semiconductor data available is increasingly necessary for improving manufacturability, yield, and ultimately the reliability of end devices. But without sufficient knowledge of relationships between data from different processes and computationally efficient data structures, the value of any data is significantly reduced. In the semiconductor industry, reducing waste, decreas... » read more

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