Week In Review: Semiconductor Manufacturing, Test

Export controls fallout continues; TSMC’s 3nm tapeouts; Kioxia equipping fab.


This week saw more fallout from U.S. export controls:

  • SK hynix may consider selling its memory chip production facilities in China if recently imposed controls make it too difficult to continue operations there, according to Nikkei Asia. “As a contingency plan, we are considering selling the fab, selling the equipment or transferring the equipment to South Korea,” said Kevin Noh, SK hynix chief marketing officer, while emphasizing, “We want to [continue to] operate without facing this situation.”
  • Murata president Norio Nakajima predicts the U.S. export controls will cause the worldwide supply chain to bifurcate. “The world is decoupling at a faster pace than I had feared,” he said. “It’s difficult to tell at this point how much of an impact [the export curbs] will have on the Chinese economy. We’ll do what we have been doing: Develop duplicate supply chains — one for the U.S.-led economic bloc and one for China-led bloc.”
  • ASMI expects Chinese sales to drop 40% on U.S. chip sanctions.
  • The Lingang Special Area, part of Shanghai’s free-trade zone, joined forces with Shanghai University and the city’s Integrated Circuit Industry Association to set up a new facility to train domestic talent for the Chinese semiconductor sector.

Apple is accelerating development of its second generation M2 processor despite slow PC sales. The A2 Pro processor, a.k.a. Rhodes Chop, will feature a 10 core CPU and 20 core GPU, and will be produced using TSMC’s 3nm process technology.

Vietnam is coming on strong as an electronics supplier with interest and facilities from companies such as Apple and Samsung, according to Asia Times. Between 2010 and 2020, exports of electronics, computers and components from Vietnam grew at an average annual rate of 28.6%, with double-digit growth even in the years prior to the US-China trade tensions and Covid-19 lockdowns.

Sri Samavedam, senior vice president of CMOS technologies at imec, discusses semiconductor industry trends, including details on backside power delivery.


TSMC announced the Open Innovation Platform (OIP) 3DFabric Alliance at the 2022 Open Innovation Platform Ecosystem Forum. “3D silicon stacking and advanced packaging technologies open the door to a new era of chip-level and system-level innovation, and also require extensive ecosystem collaboration to help designers navigate the best path through the myriad options and approaches available to them,” said Dr. L.C. Lu, TSMC fellow and vice president of design and technology platform. “Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers an easy and flexible way to unlocking the power of 3D IC in their designs, and we can’t wait to see the innovations they can create with our 3DFabric technologies.”

Kioxia opened a new 1 trillion-yen (U.S. $6.8 billion) flash memory fab. Fab7 at the Yokkaichi Plant in Mie Prefecture was completed in April and will begin full operation once the equipment is installed and running. The addition will raise the Yokkaichi plant’s total production capacity by 30%. With subsidies of up to 92.9 billion yen (U.S $635 million) from the Japanese government, the plant will produce 162-layer NAND flash memories, along with other next-generation products.

While the EU Chips Act continues to gain momentum, Amkor is highlighting its capability to serve  EU-based automotive industry leaders within its 500,000 square foot, IATF 16949-certified Porto facility. “Automotive semiconductor applications are evolving beyond wirebond and moving to flip chip technology,” said Kevin Engel, Amkor’s corporate vice president, Flip Chip/Wafer Services business unit. “Designs are moving to fan-out solutions with more chips integrated per package and to larger systems combining multi-die and wafer level chip scale packages that help automotive OEMs meet the challenges of the transition to smarter cars with increased connectivity and more advanced safety features,” GlobalFoundries and Infineon are among Amkor’s partners.

The Tokyo Institute of Technology WOW (wafer-on-wafer) Alliance and Taiwan’s National Cheng Kung University have agreed on a first-ever technical partnership for implementation of next-generation 3D integrated technology based on BBCube (bumpless build cube). Technology developments will focus on wafer thinning, die-to-wafer, wafer-to-wafer hybrid bonding, microTSVs, and more. Plans to achieve commercialization by 2025 will proceed through the BBCube business alliance.

MIT created a die bonder simulation, which students can use to practice tool usage. The VR die bonder is one of 40 simulations of advanced manufacturing tools planned for the Virtual Manufacturing Lab (VM-Lab), a three-year collaboration between researchers at MIT, Clemson University, and the University of Arizona.

Siemens Digital Industries’ Teamcenter software for Product Lifecycle Management (PLM) is now available on Google Cloud. Additionally,  Siemens introduced Capital Electra X, a cloud-native electrical design SaaS offering aimed at individual electrical designers or small teams.

TSMC has certified a broad array of EDA solutions from Siemens Digital Industries Software for the foundry’s N3E (3nm) process technologies. “Our latest collaboration with Siemens can better enable next-generation silicon and system innovation for high performance computing (HPC) and mobile applications,” said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC.

Synopsys, Ansys, and Keysight accelerate 5G/6G SoC designs with new mmwave reference flow for TSMC process technology.

Synopsys announced the availability of EDA and IP solutions for 2D/2.5D/3D multi-die systems for TSMC’s N7, N5 and N3 process technologies. In addition, the flows and Synopsys’ broad Foundation and Interface IP portfolio have achieved multiple successful tapeouts on the TSMC N3E process. The collaborative efforts on the advanced process technology also extend to analog design migration, AI-driven designs, and physical verification scaling in the cloud.

JCET announced its financial results for the third quarter of 2022. “In the first three quarters of this year, the revenue and profit from JCET’s high-density system-level packaging technology and fan-out wafer level packaging technology increased significantly compared with the same period last year, reflecting the significant growth in the large-scale application of semiconductor heterogeneous integrated packaging in computers, new energy vehicles, smart cars, intelligent manufacturing, and other fields,” said JCET CEO Li Zheng. “JCET will further increase its resource investment in relevant technologies and markets and is confident to continue strengthening its leading position in the global high-performance packaging market.”

UMC was named “Best Silicon Foundry (CMOS)” by Infineon.

Capital equipment

KLA introduced the Orbotech Corus 8M direct imaging (DI) solution. Combining increased resolution with high accuracy to pattern finer lines, the extendable Orbotech Corus DI platform uniquely supports double-sided imaging in a fully automated solution. “The all new Orbotech Corus DI platform provides precise line forming capability at manufacturing throughput speeds and has achieved proven success in customer deployments,” said Arik Gordon, general manager of the LIS division at KLA. “Our continued investments in precision DI technology will extend to future Orbotech Corus Series offerings as well, with additional enhancements planned for higher accuracy and resolution in upcoming years to continue enabling the IC substrate technology roadmap.”

Advantest announced the latest addition to its Extended Power Supply (XPS) card series — the DC Scale XPS128+HV, which combines 128 channels per card with per-channel voltage ranges of up to +24V. “Our customers are increasingly asking for solutions that can perform multisite parallel test of PMICs with multiple high-current power domains,” said Jürgen Serrer, general manager and executive vice president of Advantest’s V93000 Business Unit. “With its full four-quadrant operation, high channel count and extended voltage ranges, the XPS128+HV is an excellent fit for testing high-voltage PMIC applications.”


A Harvard Business Review study concluded that a disruption of a Taiwanese fab for 10 days could cause additional disruptions across the entire supply chain that would last almost a year. They offer suggestions on building resilience.

Scientists with the University of Chicago have discovered a way to create a material that flows like a glass but conducts electricity like a metal. Their paper “Intrinsic glassy-metallic transport in an amorphous coordination polymer,” explores the material’s properties.

 The NSF issued a solicitation to “prepare, nurture, and grow the national scientific research workforce for creating, utilizing, and supporting advanced cyberinfrastructure to enable and potentially transform fundamental science and engineering research and education and contribute to the Nation’s overall economic competitiveness and security.”

 Further reading

Are you ready for a 5.5D package? In our new video, Vidya Neerkundar of Siemens EDA discusses the latest packaging architectures, IEEE Standard 1838, and the associated testing challenges.

Find the latest chip industry earnings releases here. Although most companies reported revenue growth, this latest round of chip industry earnings releases reflected a few major themes.

Check out our Test, Measurement & Analytics and Manufacturing, Packaging, & Materials newsletters for these highlights and more:

Upcoming events:

  • ICCAD 2022, Oct. 30-Nov.4 (San Diego, CA)
  • SMTA International 2022, Oct. 31-Nov. 1 (Minneapolis, MN)
  • SEMI Pacific Northwest Forum, Nov. 3 (Beaverton, OR)
  • International Supercomputing Conference SC22, Nov. 12-18 (Dallas, TX)
  • Electronica 2022, Nov. 15-18 (Munich, Germany)
  • Materials Research Society, Nov. 27-Dec. 2 (Boston, MA)
  • IEEE International Electron Devices Meeting, Dec. 3-7 (San Francisco, CA)
  • First Annual Chiplet Summit, Jan. 24-26, 2023 (San Jose, CA)

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