Use Tcl To Save Signals More Efficiently In AMS Simulations


Saving signal waveforms during a simulation is one of the basic ways to check the simulation results. However, with large SoC designs, it’s not always practical to save all signals during simulation, and the simulation performance might also be impacted by the number of signals being saved. Therefore, a crucial part of the simulation setup is to specify the expected and essential signals to s... » read more

Electro-Thermal Design Breakthrough


Electronic component manufacturers have traditionally provided models in SPICE format, so customers can simulate their application circuits and better understand the features, capabilities, and interactions of those parts in the system context. Now, with BCI ROM, a similar and parallel thermal model supply chain can develop. This technology breakthrough arrives at a time of component design-in ... » read more

RL-Guided Detailed Routing Framework for Advanced Custom Circuits


A technical paper titled "Reinforcement Learning Guided Detailed Routing for Custom Circuits" was published by researchers at UT Austin, Princeton University, and NVIDIA. "This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. C... » read more

Learning The AMS Circuit Representation From Layout Positions (UT Austin/ NVIDIA)


A recent technical paper titled "TAG: Learning Circuit Spatial Embedding From Layouts" was published by researchers at UT Austin and NVIDIA. Abstract "Analog and mixed-signal (AMS) circuit designs still rely on human design expertise. Machine learning has been assisting circuit design automation by replacing human experience with artificial intelligence. This paper presents TAG, a new parad... » read more

Digitizing Memory Design And Verification To Accelerate Development Turnaround Time


By Anand Thiruvengadam, Farzin Rasteh, Preeti Jain, and Jim Schultz Some digital design and verification engineers imagine that their colleagues working on analog/mixed-signal (AMS) chips are jealous. After all, the digital development flow has enjoyed the benefits of increased automation and higher levels of abstraction for many years. Hand-instantiated devices and manual interconnection we... » read more

Reliability Concerns Shift Left Into Chip Design


Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

AnastASICA — Towards Structured and Automated Analog/Mixed-Signal IC Design For Automotive Electronics


In our world based on electronics, the design of analog/mixed-signal (AMS) ICs is still mainly done manually. While digital design benefits from complete synthesis flows, analog lags far behind in terms of development time, cost, and risk. Analog design flows are hardly standardized and necessitate the four eye principle as important quality tool. Thus, highly experienced designers who incorpor... » read more

Week In Review: Auto, Security, Pervasive Computing


The American Foundries Act, a bipartisan initiative to revive U.S. leadership in the global microelectronics sector, was announced by U.S. Democratic Senator Chuck Schumer from New York. “The economic and national security risks posed by relying too heavily on foreign semiconductor suppliers cannot be ignored, and Upstate New York, which has a robust semiconductor sector, is the perfect place... » read more

Week In Review: Auto, Security, Pervasive Computing


Edge, cloud, data center Programmable logic company Efinix used Cadence’s Digital Full Flow to finish Efinix’s Trion FPGA family for edge computing, AI/ML and vision processing applications, according to a press release. Last week Efinix also announced three software defined SoCs based on the RISC-V core. The SoCs are optimized to the Trion FPGAs. AI, machine learning Amazon will tempo... » read more

Week In Review: Auto, Security, Pervasive Computing


Edge, cloud, data center Synopsys launched its USB4 IP and tools, already with a successful tapeout of a USB4 PHY test chip on 5nm advanced FinFET process. The Designware USB4 IP’s throughput is up to 20 or 40 Gbps, which Synopsys says is the bandwidth needed for high-performance edge AI, storage, PC, and tablet SoC designs. Also, Samsung Foundry certified Synopsys’ Design Compiler NXT for ... » read more

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