tag: analog design

Thinking Big: From Chips To Systems
By Ed Sperling - 27 Feb, 2024 - Comments: 0

Semiconductor Engineering sat down with Aart de Geus, executive chair and founder of Synopsys, to talk about the shift from chips to systems, next-generation transistors, and what's required to build multi-die devices in the context of rapid change and other systems. SE: What are the biggest changes you're seeing in the chip industry these days, and why now? de Geus: It's not just the siz... » read more

Which Data Works Best For Voltage Droop Simulation
By Ann Mutschler - 15 Jan, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the need for the right type of data, why this has to be done early in the design flow, and how 3D-IC will affect all of this, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, prod... » read more

Analog Design Complicates Voltage Droop
By Ann Mutschler - 27 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about voltage droop in analog and mixed-signal designs, and the need for multi-vendor tool interoperability and more precision, with Bill Mullen, distinguished engineer at Ansys; Rajat Chaudhry, product management group director at Cadence; Heidi Barnes, senior applications engineer at Keysight; Venkatesh Santhanagopalan, product ... » read more

Generating the Generator: A User-Driven And Template-Based Approach Towards Analog Layout Automation
By Fraunhofer IIS/EAS - 12 Apr, 2023 - Comments: 0

Various analog design automation attempts have addressed the shortcomings of the still largely manual and, thus, inefficient and risky analog design approach. These methods can roughly be divided into synthesis and procedural generation. An important key aspect has, however, rarely been considered: usability. While synthesis requires sophisticated constraints, procedural generators require expe... » read more

High Thermal Die-Attach Paste Development For Analog Circuits
By Amkor - 16 Jun, 2021 - Comments: 0

In recent years, various die attach (DA) materials have been developed to cope with the higher power dissipation requirements of semiconductor devices. DA materials based on metals such as solder or sintered silver (Ag) are used for very high heat generating power devices. While they show outstanding thermal performance, the mechanical properties of these materials are less than ideal. This lim... » read more

Virtuoso ADE Assembler
By Cadence - 26 May, 2021 - Comments: 0

Cadence Virtuoso ADE Assembler is an advanced design and simulation environment that extends the capabilities of Virtuoso ADE Explorer, adding all the tests needed to fully verify a design over all operational, process, and environmental conditions. As more analysis is required, users can take incremental advantage of the Virtuoso Variation Option to do more advanced statistical analysis on the... » read more

AnastASICA — Towards Structured and Automated Analog/Mixed-Signal IC Design For Automotive Electronics
By Fraunhofer IIS/EAS - 12 May, 2021 - Comments: 0

In our world based on electronics, the design of analog/mixed-signal (AMS) ICs is still mainly done manually. While digital design benefits from complete synthesis flows, analog lags far behind in terms of development time, cost, and risk. Analog design flows are hardly standardized and necessitate the four eye principle as important quality tool. Thus, highly experienced designers who incorpor... » read more

Plan-Based Analog Verification Methodology
By Cadence - 27 May, 2020 - Comments: 0

The ability to verify all the aspects of an analog design and to keep track of all the different verification tasks is a growing challenge. Manual attempts to do so often lead to mistakes since they rely on constantly updated documents. The Cadence Virtuoso ADE Verifier provides an overarching verification plan that links to all analog tests across multiple designers. The Virtuoso ADE Verifier ... » read more

Managing Analog Designs For Successful Tapeouts
By Cliosoft - 06 Nov, 2019 - Comments: 0

Managing analog designs beyond data management to IP reuse and beyond in order to create a collaborative platform for design management from concept-to-GDSII. Click here to read more. » read more

Why Analog Designs Fail
By Brian Bailey - 14 Feb, 2019 - Comments: 2

The gap between analog and digital reliability is growing, and digital designs appear to be winning. Reports show that analog content causes the most test failures and contributes significantly more than digital to field returns. The causes aren't always obvious, though. Some of it is due to the maturity of analog design and verification. While great strides have been made in digital circuit... » read more

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