tag: analog

Executive Insight: Aart de Geus
By Ed Sperling - 10 Aug, 2015 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to talk about acquisitions, software and EDA. What follows are excerpts of that interview, which was conducted in front of a live audience at DAC. SE: A lot of Synopsys' investments are moving in a new direction, namely software. Why is that becoming so important to your company? De Geus: It's not a dif... » read more

Analog Evolves Into Mixed Signal
By Linh Hong - 06 Aug, 2015 - Comments: 0

Predictions about the Internet of Things suggest this may be the new “Killer App,” something the semiconductor industry has long been looking for. Reinforcing the forecasts are television commercials from companies such as Cisco and GE touting the IoT’s impact on everything from jet engines to robots, capturing everyone’s imagination. New categories of products such as smartwatches will... » read more

Analog FastSpice Platform Full-Spectrum Sampled Periodic Noise Analysis
By Mentor, a Siemens Business - 29 Jul, 2015 - Comments: 0

Many high-performance analog/mixed-signal ICs include track-and-hold circuits to sample analog signals at one or more discrete timepoints per period. Although track-and-hold circuits are periodic, traditional periodic noise (pnoise) analysis does not apply because it measures the device noise impact integrated over an entire period rather than at instantaneous time points within the target peri... » read more

Moore Memory Problems
By Brian Bailey - 09 Jul, 2015 - Comments: 0

The six-transistor static memory cell (SRAM) has been the mainstay of on-chip memory for several decades and has stood the test of time. Today, many advanced SoCs have 50% of the chip area covered with these memories and so they are critical to continued scaling. “The SRAM being used in modern systems is similar to the SRAM they were using in the 1970s and 1980s,” says Duncan Bremner, ch... » read more

SoC Integration Headaches Grow
By Ed Sperling - 16 Jun, 2015 - Comments: 0

As the number of IP blocks grows, so do the headaches of integrating the various pieces and making sure they perform as planned within a prescribed power envelope. This is easier said than done, particularly at the most advanced process nodes. There are more blocks, more power domains, more states and use-model dependencies, and there is much more contention for memories. There are physical ... » read more

Analog’s Day Of Reckoning
By Brian Bailey - 16 Jun, 2015 - Comments: 0

The numbers being touted by the semiconductor industry for IoT edge devices are staggering. How they are going to be used, who will make them, or indeed who will make money from them are much less certain. The industry seems to be clear about the content of these devices. A small processor, some flash memory or possibly even some of the new memory technologies that are coming along, a radio ... » read more

Next-Generation Parasitic Extraction For 16nm And Beyond
By Mentor, a Siemens Business - 21 May, 2015 - Comments: 0

Advanced nodes and innovative process features such as finFET transistors require a leap forward in the performance and accuracy of analysis tools. The new Calibre xACT solution is a high-performance, high-accuracy parasitic extraction tool architected from the top-down for diverse IC design styles at advanced nodes. The Calibre xACT product delivers reference-level accuracy for leading-edge fi... » read more

Pressure Builds To Revamp The Design Flow
By Ed Sperling - 23 Apr, 2015 - Comments: 1

Without [getkc id="7" kc_name="EDA"] there would be no [getkc id="74" comment="Moore's Law"] as we know it today, and without Moore's Law there would be a much more limited need for EDA. But after more than three decades of developing design flows packed with sophisticated tools to automate semiconductor design through verification, and thereby enable feature shrinks that are the basis of Moore... » read more

High-Performance Analog And RF Circuit Simulation Using The Analog FastSPICE Platform At Columbia University
By Mentor, a Siemens Business - 22 Apr, 2015 - Comments: 0

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Areas of research include design techniques for circuits operating below 1 V, digitally calibrated RF front ends for superior linearity performance, LO synthesizers for wireless applications,... » read more

High-Performance Analog And RF Circuit Simulation Using The Analog FastSPICE Platform At Columbia University
By Mentor, a Siemens Business - 08 Apr, 2015 - Comments: 0

The research group led by Professor Peter Kinget at the Columbia University Integrated Systems Laboratory (CISL) focuses on cutting edge analog and RF circuit design using digital nanoscale CMOS processes. Areas of research include design techniques for circuits operating below 1 V, digitally calibrated RF front ends for superior linearity performance, LO synthesizers for wireless applications,... » read more

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