tag: analog

112G SerDes Reliability
By Ed Sperling - 05 Oct, 2020 - Comments: 0

Priyank Shukla, product marketing manager at Synopsys, digs into 112Gbps SerDes, why it’s important to examine the performance of these devices in the context of a system, what is acceptable channel loss, and how density can affect performance, power and noise. » read more

Integrity Problems For Edge Devices
By Brian Bailey - 14 Sep, 2020 - Comments: 0

Battery-powered edge devices need to save every picojoule of energy they can, which often means running at very low voltages. This can create signal and power integrity issues normally seen at the very latest technology nodes. But because these tend to be lower-volume, lower-cost devices, developers often cannot afford to perform the same level of analysis on these devices. Noise can come in... » read more

Analog Chip Layout: Creativity Vs. Deadlines
By Benjamin Prautsch - 10 Sep, 2020 - Comments: 0

The entire design of integrated circuits, from the specification onward, depends on successful validation by measurement of microchips. One key milestone in this process is the completion of the layout. However, the path to reach this point can be quite difficult as many iterations are usually required. It includes: Iterations with the customer to finalize the specification. Iteratio... » read more

Essential Analog IC Information On-The-Go
By Anil Telikepalli - 03 Sep, 2020 - Comments: 0

Ever find that you need to review a technical detail or look up IC specs, but you're not in front of your computer? Whether you are sheltering in place at home, working in the lab, or walking outside to get fresh air, Maxim Integrated has developed a way to bring analog expertise directly into your hands. Our new Essential Analog mobile app, available for iOS and Android, provides quick and ... » read more

What’s Next For Semis?
By Mark LaPedus - 20 Aug, 2020 - Comments: 0

It’s been a turbulent year in the semiconductor industry. 2020 was supposed to be a strong year. Then, the coronavirus outbreak hit. Suddenly, a large percentage of countries implemented various measures to mitigate the outbreak, such as stay-at-home orders as well as business and store closures. Economic turmoil and job losses soon followed, not to mention the human tragedy involved. M... » read more

Problems And Solutions In Analog Design
By Ann Mutschler - 05 Aug, 2020 - Comments: 1

Advanced chip design is becoming a great equalizer for analog and digital at each new node. Analog IP has more digital circuitry, and digital designs are more susceptible to kinds of noise and signal disruption that have plagued analog designs for years. This is making the design, test and packaging of SoCs much more complicated. Analog components cause the most chip production test failures... » read more

Fast And Accurate Variation-Aware Mixed-Signal Verification Of Time-Domain 2-Step ADC
By Mentor, a Siemens Business - 08 Jul, 2020 - Comments: 0

To meet today’s analog-to-digital converter (ADC) specifications and to produce a high-yield design, teams typically need to perform extensive brute force mixed-signal simulations to account for all potential design variation. However, at nanometer nodes, the number of process, voltage and temperature (PVT) corners and parametric variation grow exponentially making the simulation impractical ... » read more

Data Becomes Key For Next-Gen Chips
By Susan Rambo And Ed Sperling - 07 Jul, 2020 - Comments: 1

Data has become vital to understanding the useful life of a semiconductor — and the knowledge gleaned is key to staying competitive beyond Moore’s Law. What's changed is a growing reliance earlier in the design cycle on multiple sources of data, including some from further right in the design-through-manufacturing flow. While this holistic approach may seem logical enough, the semiconduc... » read more

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification
By Greg Curtis - 25 Jun, 2020 - Comments: 0

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

Aging Problems At 5nm And Below
By Brian Bailey - 11 Jun, 2020 - Comments: 3

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed. As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential par... » read more

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