tag: Ansys Apache

Are Processors Running Out Of Steam?
By Ed Sperling - 24 Feb, 2014 - Comments: 1

Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

Blog Review: Feb. 19
By Ed Sperling - 19 Feb, 2014 - Comments: 0

Adding a GUI to an RTOS? It may sound counterintuitive, but Mentor’s Colin Walls looks at why and where they’re being used. Cadence’s Richard Goering infuses some humor into signal integrity, which could definitely use it, courtesy of Eric Bogatin and Henny Youngman. When was the last time you saw a signal integrity engineer rolling on the floor in hysterical laughter? Well, there’s ... » read more

The Week In Review: System-Level Design
By Ed Sperling - 14 Feb, 2014 - Comments: 0

Cadence bought TranSwitch’s high-speed interface IP assets. TranSwitch, which made chips for communications equipment, filed for bankruptcy in November. (The company’s Web site is no longer active.) Cadence also won a deal with Microsoft, which will use Tensilica processors in the new Xbox One audio subsystem. And Cadence rolled out HiFi Audio Tunneling for Android, which takes advantage of... » read more

Schedule Versus Specifications
By Ann Mutschler - 14 Feb, 2014 - Comments: 0

With power being paramount in SoCs today, I was surprised to hear the amount of time spent on power reduction exercises can be only a few days. According to William Ruby at Ansys/Apache, how much time engineers spend on power reduction activities depends on how sensitive the design is to power and whether they are still trying to meet the power spec or -- based on the early power estimates �... » read more

Power Reduction Through Sequential Optimization
By Ann Mutschler - 13 Feb, 2014 - Comments: 1

Dealing with power is a multifaceted challenge and is an equal-opportunity problem — everybody can contribute to the solution and at many levels of abstraction. At the architectural or system level, fundamental tradeoffs are done and the engineering team decides how much memory the system needs, what type of processor, what performance, area, power, among other things. Some people may use ... » read more

Heat Problems Grow With FinFETs, 3D-ICs
By Ann Mutschler - 13 Feb, 2014 - Comments: 2

From high-end consumer devices to rack-mounted arrays inside of data centers, thermal issues are becoming more serious—and getting much more attention. Driving this shift is the move from single chips to 3D ICs, whether they are interposer-based or stacked die. It’s a well-understood challenge: Die stacking can cause thermal issues because of the lack of a readily accessible thermal diss... » read more

ESD Signoff No Longer A “Nice to Have” In FinFET Design Era
By Karthik Srinivasan - 13 Feb, 2014 - Comments: 0

As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of their existing ESD protection strategy. With significant complexity embedded in the silicon, failure analysis and silicon debug is challenging and time consuming even to the ESD experts. Technology ... » read more

Full-Chip IC ESD Integrity
By Various Writers - 12 Feb, 2014 - Comments: 0

ESD or electro-static discharge induced field failures for integrated circuits (IC) has always been an challenge. Literature survey indicates that as high as 35% of total chip field failures are ESD related. Several trends in the IC industry are exacerbating the impact of ESD induced failures: (a) move towards advanced processing technologies with shrinking geometries, (b) push for higher... » read more

The Road Ahead for 2014: Semiconductors
By Brian Bailey - 23 Jan, 2014 - Comments: 1

Last week, Semiconductor Engineering examined the 2014 predictions from several thought leaders in the industry and published those predictions that related to general market trends. Many of those predictions require some advances in semiconductor technologies and fabrications capabilities. It is those predictions that will be examined in this part, followed next week by the predictions related... » read more

Blog Review: Jan. 22
By Ed Sperling - 22 Jan, 2014 - Comments: 0

Mentor’s Anil Khanna believes Nest’s approach should be incorporated into the entire power grid. The ramifications of that are interesting to ponder. Speaking of Nest, Cadence’s Brian Fuller looks at the implications of the $3.2 billion acquisition of the company by Google. Will Google get it right? Maybe. Synopsys’ Richard Solomon has come up with a new definition for New Year’... » read more

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