tag: Ansys Apache

How Reliable Are Interconnects In 16nm FinFET Designs?
By Arvind Vel - 05 Dec, 2013 - Comments: 0

The 16nm FinFET process node is rapidly becoming the preferred choice for advanced Integrated Circuit (IC) designs. The 16nm node’s lower standby leakage characteristics and increased drive strength capability enable IC designers to push the boundaries of low power – high performance designs. However, the choice of the node is also accompanied by reduced reliability margins, requiring desig... » read more

Thermally Challenged
By Brian Bailey - 05 Dec, 2013 - Comments: 0

Chips run hot and the thermal densities increase with every reduction in fabrication geometry. “When we go down to 16nm the local power density increases by 25% and the local gate density also increases by 25% to 30%,” explains Norman Chang, vice president of product strategy at Ansys/Apache. In fact, this is becoming such a large problem that it is affecting the scaling process itsel... » read more

Powerful Software Optimization
By Brian Bailey - 05 Dec, 2013 - Comments: 0

It is commonly accepted that the higher you go in the design chain, the bigger the impact that design and implementation decision can have. While power optimization may have started deep in the silicon, the success of a product, such a smart phone, often is based on the time between charges. Batteries provide a finite energy resource, and while low-level optimization may focus on power reductio... » read more

Blog Review: Sept. 18
By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

New Risk Factors For SoCs
By Ed Sperling - 12 Sep, 2013 - Comments: 0

By Ed Sperling Third-party IP is becoming increasingly important in SoC designs. It saves development time and adds unique value. It also can improve performance and lower power, because a company specializing in IP frequently can build and optimize it better than a company that builds entire chips. But there are also plenty of landmines in IP integration, and there is a growing concern abo... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

Power Grid Analysis Heats Up At 20nm
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

Bubble Gum and Scotch Tape
By Ann Mutschler - 12 Jul, 2012 - Comments: 0

It’s always extremely interesting to talk with actual design engineers, trudging through the trenches of challenges like 3D design. Recently, I was able to speak with Robert Patti, chief technology officer, vice president of design engineering and a director at Tezzaron Semiconductor. The company has been putting 3D designs together for quite some time so I expected to hear that they are u... » read more

Tech Talk: Power Issues Ahead
By Ed Sperling - 31 May, 2012 - Comments: 0

Aveek Sarkar, vice president of technology and support at ANSYS Apache, talks with Low-Power Engineering about growing concerns over electrostatic discharge, electromigration, the impact of stacked die, and the need for power and thermal models. [youtube vid=-7TtszsuZP0] » read more

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