tag: ANSYS

2.5D Timetable Coming Into Focus
By Ed Sperling - 23 Oct, 2014 - Comments: 0

After years of empty promises, the timetable for [getkc id="82" kc_name="2.5D"] is coming into better focus. Large and midsize chipmakers are behind it, real silicon is being developed, and contracts are being signed. That doesn't mean all of the pieces are in place or that market uptake is at the neck of the hockey stick. And it certainly doesn't mean the semiconductor industry is going to ... » read more

Blog Review: Oct. 22
By Ed Sperling - 22 Oct, 2014 - Comments: 0

What is UX? The User Experience, of course. Rambus' Aharon Etengoff notes that the IoT UX is now the subject of a Harvard Business Review article. A long list of hurdles are expected at the 10nm process node, including multiple levels of local interconnects, more complex layout rules, timing problems, and a slew of others. Cadence's Richard Goering puts it all in perspective. Mentor's R... » read more

Blog Review: Oct. 15
By Ed Sperling - 15 Oct, 2014 - Comments: 0

Obesity makes your liver age faster, but you'll need a sophisticated biological clock to see that. Ansys' Bill Vandermark uncovers the top 5 engineering articles of the week. This one includes cyborg horses and an implanted prosthetic arm. Mentor's Colin Walls takes a look at "hard" and "soft" real time. It sounds like something out of a Salvador Dali painting. Rambus' Aharon Etengoff t... » read more

Architecture Versus Silicon
By Ann Mutschler - 09 Oct, 2014 - Comments: 0

For many, if not most designs today, power is everything. Determining where power is being lost is critical to making sure the design is optimized. So where to begin? To this end, it is useful to go back to the fundamentals of what power is and what power consumption is, noted Paul Traynar, software architect at [getentity id="22021" comment="ANSYS/Apache"]. “Power is proportional to capac... » read more

Optimizing Analog For Power At Advanced Nodes
By Ann Mutschler - 09 Oct, 2014 - Comments: 0

As any engineering manager will tell you, analog and digital engineers seem like they could be from different planets. While this has changed somewhat over time, [getkc id="52" comment="analog"] is still something of a mystery to many in [getkc id="81" kc_name="SoC"] design teams. Throw power management into the mix and things really get interesting. Improvements in analog/mixed-signal tools... » read more

Ubiquitous Trend In Design for Power (DFP) For IP And SoCs
By Vic Kulkarni - 09 Oct, 2014 - Comments: 0

Semiconductor design engineers must meet power specification thresholds, or power budgets, that are dictated by the electronic system vendors to whom they sell their products. Analyzing and reducing power across the board in all market segments has become a key requirement and a differentiator, especially over last 8 to 10 years for IP and IP-based SoC designers. Many products live and die due ... » read more

Energy Boost For Power Standards
By Brian Bailey - 09 Oct, 2014 - Comments: 0

If the amount of standards work and industry effort that is being expended on a given topic is any indicator of the growing importance of a design concern, then power has most certainly become the hottest topic in the industry. Thankfully, it seems as if everyone has learned their lessons from the CPF/[gettech id="31044" t_name="UPF"] struggles and is attempting to coordinate activities, while ... » read more

System-Aware SoC Power, Noise And Reliability Sign-off
By Ansys - 08 Oct, 2014 - Comments: 0

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

Blog Review: Oct. 8
By Ed Sperling - 08 Oct, 2014 - Comments: 0

Mentor's Robin Bornoff examines the thickness of leg hair and just how much of a drag it causes for bicyclists. More hair equals more drag, and thicker hair is worse. Ansys' Justin Nescott routes out the top five engineering articles of the week. Of particular note: The world's most precise clock, which loses one second every 13.8 billion years. Cadence's Richard Goering puts some conte... » read more

Blog Review: Sept. 24
By Ed Sperling - 24 Sep, 2014 - Comments: 0

Cadence’s Brian Fuller captures Chris Rowen’s phylum classifications for data-efficient design—lots of insects and much bigger but fewer mammals. There are cognitive layers in between, as well. Check out the chart. Mentor’s Robin Bornoff digs into thermal runaway and how to determine when it will occur—and burn up a chip. There’s a video to illustrate just what can go wrong. ... » read more

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