Chip Industry Week In Review


Absolics, an affiliate of Korea materials company SKC, will receive up to $75 million in direct funding under the U.S. CHIPS Act for the construction of a 120,000 square-foot facility in Covington, Georgia, for glass substrates in advanced packaging. imec will host a €2.5 billion (~$2.72B) pilot line for researching chips beyond 2nm, partially funded through the EU Chips Act. imec CEO Luc ... » read more

Blog Review: May 22


Cadence's Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens' Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain spec... » read more

Chip Aging Becoming Key Factor In Data Center Economics


Chip aging is becoming a much bigger concern inside of data centers, where it can impact server uptime, utilization rates, and the amount of energy needed to drive signals and cool entire server racks. Aging in chips is the result of both higher logic utilization and increasing transistor density. This is problematic for data centers, in general, but especially for AI chips where digital log... » read more

Will Domain-Specific ICs Become Ubiquitous?


Questions are surfacing for all types of design, ranging from small microcontrollers to leading-edge chips, over whether domain-specific design will become ubiquitous, or whether it will fall into the historic pattern of customization first, followed by lower-cost, general-purpose components. Custom hardware always has been a double-edged sword. It can provide a competitive edge for chipmake... » read more

Enabling Multiscale Simulation


As product development teams face increasingly complex challenges — including the need for greater sustainability — there’s a growing awareness of the critical contributions made by materials. Many of our most pressing engineering challenges, from renewable energy grids to green transportation, rely on identifying or creating the right materials. Historically, materials discovery, mate... » read more

Power/Performance Costs In Chip Security


Hackers ranging from hobbyists to corporate spies and nation states are continually poking and prodding for weaknesses in data centers, cars, personal computers, and every other electronic device, resulting in a growing effort to build security into chips and electronic systems. The current estimate is that 60% of chips and systems have some type of security built in, and that percentage is ... » read more

Blog Review: May 15


Cadence's Anika Sunda suggests that RISC-V has opened numerous doors for innovation and believes EDA tools can help bridge the knowledge gap and foster a growing community of RISC-V developers. Synopsys' Alessandra Costa chats with industry experts about challenges facing analog design, what's needed for multi-die designs, and the potential of AI. Siemens' Bill Ji explains why understandi... » read more

Innovating Electric Mobility: Simulation Solutions For Electric Machines


Automakers desire solutions that can easily scale to new applications of next generation vehicles. Electrified propulsion technology is one main area where EV engineers are pushing the boundaries. Electric machine design and integration choices have system-level impacts that directly influence an automaker’s time to market and even overall market adoption. With Ansys multiphysics simulatio... » read more

Chip Industry Week In Review


Synopsys refocused its security priorities around chips, striking a deal to sell off its Software Integrity Group subsidiary to private equity firms Clearlake Capital Group and Francisco Partners for about $2.1 billion. That deal comes on the heels of Synopsys' recent acquisition of Intrinsic ID, which develops physical unclonable function IP. Sassine Ghazi, Synopsys' president and CEO, said in... » read more

Blog Review: May 8


Synopsys' Manuel Mota and Michael Posner look to UCIe as a complete stack for the die-to-die interconnect in multi-die chip designs, finding it can help maintain latency while reducing power and enhancing performance along with providing assurance of interoperability. Cadence's Durlov Khan highlights the Octal SPI interface for serial NAND flash, which enables 8-bit wide high bandwidth synch... » read more

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