tag: ANSYS

Next-Gen Power Integrity Challenges
By Ed Sperling - 14 Dec, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss power integrity challenges and best practices in designs at 7nm and below, and in 2.5D and 3D-IC packages, with Chip Stratakos, partner, physical design at Microsoft; Mohit Jain, principal engineer at Qualcomm; Thomas Quan, director at TSMC; and Murat Becer, vice president at Ansys. What follows are excerpts of that conversatio... » read more

Imagining A Hydrogen-Powered Future Thanks To Simulation
By David Campbell - 14 Dec, 2023 - Comments: 0

Our world leaders have set ambitious goals for global decarbonization by 2050, with good reason. While the planet continues to heat up, global energy consumption is still rising, and most of this energy consumption is currently derived from fossil fuels. This bitter truth has inspired a wave of decarbonization trends in response — including green hydrogen, which is generated using renewable ... » read more

Blog Review: December 13
By Jesse Allen - 13 Dec, 2023 - Comments: 0

Synopsys' Charles Dittmer discusses key and emerging use cases for Bluetooth Low Energy and how combining BLE with other wireless protocols can open new avenues of functionality for application areas including automotive, hearables, and retail. Cadence's Neelabh Singh points out changes in the terminologies describing USB4 links and shows the various possible link configurations put forth by... » read more

Chip Industry Week In Review
By The SE Staff - 08 Dec, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Blog Review: Dec. 6
By Jesse Allen - 06 Dec, 2023 - Comments: 0

Cadence's Vinod Khera checks out potential implications of generative AI for EDA, including how it could increase the learning rate of students and reduce the rising verification cost. Synopsys' Kiran Vittal considers the driving factors behind RISC-V's growth and why it is becoming increasingly important for applications ranging from automotive to 5G mobile, AI, and data centers. Siemens... » read more

System State Challenges Widen
By Brian Bailey - 30 Nov, 2023 - Comments: 0

Knowing the state of a system is essential for many analysis and debug tasks, but it's becoming more difficult in heterogeneous systems that are crammed with an increasing array of features. There is a limit as to how many things engineers can keep track of, and the complexity of today's systems extends far beyond that. Hierarchy and abstraction are used to help focus on the important aspect... » read more

3D-ICs May Be The Least-Cost Option
By Brian Bailey - 30 Nov, 2023 - Comments: 1

When 2.5D and 3D packaging were first conceived, the general consensus was that only the largest semiconductor houses would be able to afford them, but development costs are quickly coming under control. In some cases, these advanced packages actually may turn out to be the lowest-cost options. With stacked die [1], each die is considered to be a complete functional block or sub-system. In t... » read more

Blog Review: November 29
By Jesse Allen - 29 Nov, 2023 - Comments: 0

Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

Chip Industry Week In Review
By The SE Staff - 17 Nov, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

Blog Review: November 15
By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

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