tag: ANSYS

Simulating Reality: The Importance Of Synthetic Data In AI/ML Systems For Radar Applications
By Arien Sligar - 09 Feb, 2023 - Comments: 0

Artificial intelligence and machine learning (AI/ML) are driving the development of next-generation radar perception. However, these AI/ML-based perception models require enough data to learn patterns and relationships to make accurate predictions on new, unseen data and scenarios. In the field of radar applications, the data used to train these models is often collected from real-world meas... » read more

Blog Review: Feb. 8
By Jesse Allen - 08 Feb, 2023 - Comments: 0

Cadence's Sanjeet Kumar points to key changes and optimizations that are done for USB3 Gen T compared to USB3 Gen X tunneling in order to minimize tunnel overhead and maximize USB3 throughput. Siemens EDA's Harry Foster considers the effectiveness of IC and ASIC verification by looking at schedule overruns, number of required spins, and classification of functional bugs. Synopsys' Chris C... » read more

Best Practice: RANS Turbulence Modeling In Ansys CFD
By Ansys - 08 Feb, 2023 - Comments: 0

Turbulence modeling is one of the main sources of uncertainty in CFD simulations of technical flows. This is not surprising, as turbulence is the most complex phenomenon in classical physics. Turbulent flows pose a multi-scale problem, where the dimension of the technical device is often of the order of meters (or even 102 meters in case of airplanes and ships), whereas the smallest turbulence ... » read more

Chip Industry’s Earnings Roundup
By Linda Christensen - 06 Feb, 2023 - Comments: 0

Editor's Note: Updated throughout February 2023 for additional earnings releases. Many companies reported revenue growth in the most recent quarter, but the latest round of chip industry earnings releases reflected some major themes: Demand for consumer electronics softened due to inflation, rising interest rates, and post-pandemic market saturation, creating a slump in the memory chip ... » read more

Blog Review: Feb. 1
By Jesse Allen - 01 Feb, 2023 - Comments: 0

Siemens EDA's Harry Foster explores trends in low power design techniques for ICs and ASICs, with 72% of design projects reported actively managing power. Synopsys' Charlie Matar, Rita Horner, and Pawini Mahajan look at the concept of reliability, availability, and serviceability (RAS) in the context of high-performance computing SoC designs and how it can be supported with silicon lifecycle... » read more

Week In Review: Design, Low Power
By Susan Rambo - 27 Jan, 2023 - Comments: 0

Electronic system design (ESD) industry revenue is up 8.9% from $3,458.2 million in Q3 2021 to $3,767.4 million in Q3 2022 according to a report from SEMI’s ESD Alliance. Read our in-depth take on what this means. In an attempt to make a viable reusable DNA biosensor probe, NIST researchers used an extremely low-power FETdeveloped at CEA-LETI to remove noise in their DNA biosensor circuitr... » read more

Power Issues Causing More Respins At 7nm And Below
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Power consumption has been a major design consideration for some time, but it is far from being a solved issue. In fact, an increasing number of designs have a plethora of power-related problems, and those problems are getting worse in new chip designs. Many designs today are power-limited — or perhaps more accurately stated, thermal-limited. A chip only can consume as much power as it is ... » read more

What Does 2023 Have In Store For Chip Design?
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

Blog Review: Jan. 25
By Jesse Allen - 25 Jan, 2023 - Comments: 0

Cadence's Shyam Sharma shares some important design and verification considerations when working with DDR5 SDRAM and DDR5 DIMM-based memory subsystems, including reset and power on initialization, speed bin compliance, and refresh, RFM, and temperature requirements. Siemens EDA's Harry Foster examines trends in adoption of languages and libraries for IC and ASIC design, testbench creation, a... » read more

Blog Review: Jan. 18
By Jesse Allen - 18 Jan, 2023 - Comments: 0

Synopsys' Dana Neustadter, Sara Zafar Jafarzadeh, and Ruud Derwig argue that we are already at an inflection point for post-quantum security because devices and infrastructure systems with longer life cycles or communicating data that must be kept confidential for an extended period need to have a path towards quantum-safe solutions. Siemens EDA's Harry Foster looks at trends in adoption of ... » read more

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