tag: Apache Design Solutions

Power Model Complexity Grows
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ed Sperling The number of factors required for an effective power model has far surpassed the capabilities of even the most detailed spreadsheet at 45nm and beyond. It has now entered the realm of complex databases and architectural tradeoffs, and those tradeoffs will become even more complex as 3D stacking takes root over the next 24 months. The idea of modeling power is hardly new, but... » read more

Packaging’s Power Play
By Ed Sperling - 13 Jan, 2011 - Comments: 0

By Ann Steffora Mutschler In the not-too-distant past packaging was not an issue IC designers had to think much about. But now, due to smaller geometries and rising complexity, managing power in the entire system has become a major concern for system architects. IC and package designers now must work closely throughout the design process to make sure no surprises come up down the road. A... » read more

What is CPS?
By Matt Elmore - 12 Jan, 2011 - Comments: 0

CPS stands for Chip-Package-System. It represents a paradigm shift from the old partitioned approach of IC design into a cohesive methodology that considers the ecology of the system as comprised of the chip, package and board. Today’s design requirements are calling for a revisit to the way we look at IC design and validation. Companies no longer can afford to view design with a silo-base... » read more

The Deafening Problem Of High-Speed I/O
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more

The Growing Legacy Of Moore’s Law
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Moore’s Law has defined semiconductor design since it was introduced in 1965, but increasingly it also has begun defining the manufacturing equipment, the cooling needed for end devices, and both the heat and performance of systems. In the equipment sector the big problem has been the delay in rolling out extreme ultraviolet (EUV). Moore’s Law will require tighter spacing... » read more

Power-Delivery Network Challenges Grow
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler Physics is forcing convergence in the SoC power delivery network, whose job is to ensure that every device on a chip has a robust and stable voltage so it can meet its expected functionality and timing. In the past, chip design, package design and board design were separate disciplines, guard-banded to ensure that all the parts worked well together. Today, given t... » read more

Making Too Much Noise
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ed Sperling For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change. Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signal... » read more

Estimating Power From Mobile Device Apps
By Ann Mutschler - 09 Sep, 2010 - Comments: 0

By Ann Steffora Mutschler How do software application developers – even the ones sitting at home on their living room sofas with laptops – measure the power consumption of their application on the target device? This is a big problem today (something that is painfully obvious to owners of iPhones or Blackberries), and it will only get bigger. Software engineers may think it is not their... » read more

Changes In The Ecosystem
By Ed Sperling - 09 Sep, 2010 - Comments: 0

By Ed Sperling For the better part of two decades, semiconductor companies have been talking about ecosystems mostly for marketing and economic reasons. They’re now talking thinking about ecosystems for complex technology reasons that involve integrated models for power, transactions and manufacturability. In the late 1990s, IBM began assembling its own loose ecosystem as a way of shieldi... » read more

PathFinder: A Dynamic And Static Analysis Solution For IP And Full-Chip IC ESD Integrity
By Various Writers - 13 Aug, 2010 - Comments: 0

ESD or electro-static discharge induced field failures for integrated circuits (IC) has always been an challenge. Literature survey indicates that as high as 35% of total chip field failures are ESD related. Several trends in the IC industry are exacerbating the impact of ESD induced failures: (a) move towards advanced processing technologies with shrinking geometries, (b) push for higher le... » read more

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