tag: Apache Design

RTL Design-For-Power Methodology
By Various Writers - 14 Feb, 2013 - Comments: 0

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To download this white paper, click here. » read more

Clean Your Clock
By William Ruby - 14 Feb, 2013 - Comments: 0

Lowering power consumption seems to be on every designer’s mind these days. And yet when asked about applying low-power design techniques, many engineers respond, “Well, we do clock gating ... and that’s about it.” Clock gating is low-hanging fruit when it comes to low-power design. Clock gating is also well automated, as witnessed by capabilities in modern logic synthesis tools. The... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 09 Feb, 2013 - Comments: 0

Low-Power Engineering sat down to discuss the problems of identifying and verifying power issues with Barry Pangrle, solutions architect for low-power design at Mentor Graphics; Krishna Balachandran, director of low-power verification marketing at Synopsys; Kalar Rajendiran, senior director of marketing at eSilicon; Will Ruby, senior director of technical sales and support at Apache Design; and... » read more

First Silicon At 14nm
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ed Sperling The first 14nm test chips are beginning to roll out the door from foundries, and companies are beginning to trumpet their success. But before anyone pops the champagne corks, there are some caveats. First of all, what most people are billing as 14nm chips are actually mostly 20nm. They are readily willing to concede that point, settling on 16nm, but the reality is that it’s... » read more

All Things To All Customers
By Ed Sperling - 17 Jan, 2013 - Comments: 0

By Ann Steffora Mutschler Low-Power High-Performance Engineering recently spoke with Suresh Menon, VP of systems development at Lattice Semiconductor, about the challenges of directing the development of power-sensitive FPGAs from architectural decisions to identifying the target applications. What follows are excerpts of that discussion. LPHP: When you look at the products that Lattic... » read more

ANSYS And Apache Technologies For An Integrated Chip-Package-System Flow
By Various Writers - 17 Jan, 2013 - Comments: 0

This paper presents solutions for effectively managing design specifications (performance) and margins (price). It discusses solutions based on accurate and predictive simulation software from ANSYS and Apache that offers electronics designers a simulation-driven chip–package–system convergence methodology. To download this white paper, click here. » read more

Reducing Cost And Mitigating Risk
By Aveek Sarkar - 17 Jan, 2013 - Comments: 0

By Aveek Sarkar & Lawrence Williams How will you design your next generation of products and keep pace with rapidly evolving market needs, while managing your margins? Many industries face these same design challenges. The speed of new product development—especially for meeting complex new design requirements—has never been more demanding. Historically, the rise in product development ... » read more

RTL Design-for-Power Methodology
By Various Writers - 06 Dec, 2012 - Comments: 0

This white paper presents a design-for-power methodology, beginning early in the design process at the RTL-level for maximum impact on power. To view this white paper, click here. » read more

Waste Not, Want Not
By William Ruby - 05 Dec, 2012 - Comments: 0

Power is the new timing …. performance per watt … low-power design ... power performance trade-offs … the list of terms goes on and on, but there is no denying that power has now become the primary design objective. So what does it really take to manage power in a modern system-on-a-chip (SoC) design? Power is an “equal opportunity problem,” and all can contribute to the solution. ... » read more

The Growing Integration Challenge
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

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