Complex Tradeoffs In Inferencing Chips


Designing AI/ML inferencing chips is emerging as a huge challenge due to the variety of applications and the highly specific power and performance needs for each of them. Put simply, one size does not fit all, and not all applications can afford a custom design. For example, in retail store tracking, it's acceptable to have a 5% or 10% margin of error for customers passing by a certain aisle... » read more

Foundational Changes In Chip Architectures


We take many things in the semiconductor world for granted, but what if some of the decisions made decades ago are no longer viable or optimal? We saw a small example with finFETs, where the planar transistor would no longer scale. Today we are facing several bigger disruptions that will have much larger ripple effects. Technology often progresses in a linear fashion. Each step provides incr... » read more

The New Disruptive Force In High-End AIoT Markets


MediaTek is known for its SoC solutions in the mobile and consumer device markets. In fact, the smartphone market is now producing the most advanced and performant SoC designs on the planet. MediaTek is a vital part of this innovation. Each year it produces a range of chipsets for the mobile market, like the flagship Dimensity 9000 which adopted Arm’s v9 CPU and Mali-GPU technologies to del... » read more

PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangement


Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with m... » read more

Blog Review: Oct. 12


Synopsys' Richard Solomon, Madhumita Sanyal, and Gary Ruggles take a look at the possibilities that CXL 3.0 can bring to a variety of data-driven applications that demand increasingly higher levels of memory capacity, with higher bandwidth, more security, and lower latency. Siemens EDA's Rich Edelman provides some tips for debugging UVM testbenches, such as how to determine what line changed... » read more

Week in Review: Design, Low Power


Could power beams be the key to smart city infrastructure and 5G/6G connectivity? A new report says both lasers and microwaves offer possible paths forward in this area, though both technologies come with benefits and drawbacks. Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are desi... » read more

Auto Safety Tech Adds New IC Design Challenges


The role of AI/ML in automobiles is widening as chipmakers incorporate more intelligence into chips used in vehicles, setting the stage for much safer vehicles, fewer accidents, but much more complex electronic systems. While full autonomy is still on the distant horizon, the short-term focus involves making sure drivers are aware of what's going on around them — pedestrians, objects, or o... » read more

The Automotive Paradigm Shift


We are currently experiencing a pivotal moment concerning the automotive industry. Three major technology areas are converging. First, there is an enormous demand for advanced driver-assistance systems (ADAS) coupled with the increasing trend toward autonomy. Second is the digitization and electrification of everything, which is driving the need for efficient compute. Third is the trend to high... » read more

Blog Review: Oct. 5


Arm's Andrew Pickard chats with Georgia Tech's Azad Naeemi and Da Eun Shim about an effort to evaluate the benefit of new interconnect materials and wire geometry and determine their impacts at the microprocessor level. Synopsys' Shekhar Kapoor shares highlights from a recent panel exploring the promises, challenges, and realities of 3D IC technology, including the potential of 3D nanosystem... » read more

IC Architectures Shift As OEMs Narrow Their Focus


Diminishing returns from process scaling, coupled with pervasive connectedness and an exponential increase in data, are driving broad changes in how chips are designed, what they're expected to do, and how quickly they're supposed to do it. In the past, tradeoffs between performance, power, and cost were defined mostly by large OEMs within the confines of an industry-wide scaling roadmap. Ch... » read more

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