Balancing Memory And Coherence: Navigating Modern Chip Architectures

By Frank Schirrmeister - 21 Dec, 2023 - Comments: 0

In the intricate world of modern chip architectures, the "memory wall" – the limitations posed by external DRAM accesses on performance and power consumption growing slower than the ability to compute data – has emerged as a pivotal challenge. Architects must strike a delicate balance between leveraging local data reuse and managing external memory accesses. While caches are critical for op... » read more

Design Complexity In The Golden Age Of Semiconductors

By Frank Schirrmeister - 24 Aug, 2023 - Comments: 0

While writing last month's blog that used some of the trend charts we have seen, I noticed that a lot of the data ends in 2020 or earlier, but I was too close to the deadline to sit down and make orderly updates to some of the charts. Working day-to-day in the area of SoC integration and networks-on-chips (NoCs), the classic chart based on Karl Rupp's now 50 years of processor data that overlay... » read more

Shift Left, Extend Right, Stretch Sideways

By Brian Bailey - 27 Jul, 2023 - Comments: 0

The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

DAC 2023: Megatrends And The Road Ahead For Design Automation

By Frank Schirrmeister - 27 Jul, 2023 - Comments: 0

As Silicon Valley is in the midst of the heat wave the world is experiencing, the recent Design Automation Conference and its exhibition discussed hot technologies. Three megatrends defined the current situation – artificial intelligence (AI), chiplets, and integration. To me, the more exciting aspect of DAC was the discussion of what is ahead for EDA in the decade to come, and for that, the ... » read more

Megatrends At DAC

By Ann Mutschler - 17 Jul, 2023 - Comments: 0

Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet integration, and heterogeneous integration in an SoC and package. Frank Schirrmeister, vice president solutions and business development at Arteris IP, talks about a variety of topics that fit under the DAC umbrella... » read more

Confusion Grows Over Sensor Fusion In Autos

By Ann Mutschler - 06 Jul, 2023 - Comments: 0

A key strategy for fully autonomous vehicles is the ability to fuse together inputs from multiple sensors, which is essential for making safe and secure decisions, but it's turning out to be much harder than first imagined. There are multiple problems that need to be solved, including how to partition, prioritize, and ultimately combine different types of data, and how to architect the proce... » read more

Solving The Last-Mile Delivery Problem

By John Koon - 06 Jul, 2023 - Comments: 0

Retailers are deploying robots to cut costs and improve efficiency, opening new opportunities for chipmakers as well as a host of new challenges. Key to this strategy are autonomous roadside delivery robots (ARDRs). Retailers have been facing razor-thin profit margins for years and have turned their sights to increasing operational efficiency to stay competitive. Solving the last-mile delive... » read more

The Design Automation Conference Turns 60! What’s Hot? What’s Next?

By Frank Schirrmeister - 06 Jul, 2023 - Comments: 0

This coming week from July 9th to July 13th, experts from all over the world will descend on the Moscone Center in San Francisco to discuss aspects of what we call "Electronic Design Automation" (EDA) and typically associate with hardware development. There will be many celebratory elements this year, given the milestone of 60 years. Industry luminary Alberto Sangiovanni Vincentelli will give o... » read more

Innovative NoC Implementation Dramatically Speeds Derivative Design

By Arteris - 05 Jul, 2023 - Comments: 0

The Inuitive team faced a significant challenge when developing a derivative design based on the NU4000, their first vision-on-chip processor. The NU4000 employs the Advanced eXtensible Interface (AXI) on-chip communication bus protocol developed by Arm. However, removing one of the NU4000’s three vector cores resulted in access to only a limited number of AXI ports. The problem was that ... » read more

Not All There: Heterogeneous Multiprocessor Design Tools

By Brian Bailey - 26 Jun, 2023 - Comments: 0

The design, implementation, and programming of multicore heterogeneous systems is becoming more common, often driven by the software workloads, but the tooling to help optimize the processors, interconnect, and memory are disjointed. Over the past few years, many tools have emerged that help with the definition and implementation of a single processor, optimized for a given set of software. ... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Arteris IP