Top 5 Reasons The SoC Interconnect Matters


The on-chip interconnect is the one area of SoC design that still does not receive the priority that it deserves. It’s like Rodney Dangerfield: It gets no respect. However, that is changing because of rising chip complexity, smaller process dimensions, and acknowledgement of the fact that in a world where design teams commercially license most of the chip’s critical semiconductor IP (like C... » read more

Will The Chip Work?


As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

Can IP Integration Be Automated?


What exactly does it mean to automate [getkc id="43" comment="IP"] integration? Ask four people in the industry and you’ll get four different answers. “The key issue is how you can assemble the hardware as quickly as you can out of pre-made pieces of IP,” said Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]. To Simon Rance, senior product manager in the ... » read more

ISO 26262: Top 3 Reasons For Hardware Implementation Of Functional Safety


I’ve written articles before about ISO 26262 Certification because many SoC design teams are challenged by the barriers they have to overcome to achieve automotive functional safety, especially if they previously enjoyed success in mobility or computing but now want to shift attention to the growing array of electronics used in transportation such as automated driver assistance systems (ADAS)... » read more

The Next Level Of Abstraction For System Design


Recently there have been a lot of discussions again about the next level of design abstraction for chip design. Are we there yet? Will we ever get there? Is it SystemC? UML/SysML perhaps? I am taking the approach of simply claiming victory: Over the last 20 years we have moved up beyond RTL in various areas—just in a fragmented way. However, the human limitations on our capacity for processin... » read more

The Price Of Consolidation


Consolidation is causing far-reaching changes across the global semiconductor ecosystem due to the size of companies being bought and the dearth of startups to replenish those being acquired. Coupled with the rising cost and difficulty of shrinking features down to advanced process nodes—many argue that is the largest driver of consolidation—the market dynamics for who's buying IP, EDA t... » read more

Rethinking Differentiation


Differentiation is becoming more difficult, more time-consuming, and in some cases much more expensive for chipmakers. The traditional metrics of faster performance, lower power and less area/cost, which are leftovers from the PC era, no longer are a guarantee of success despite the fact that they are still baseline metrics for many designs. Even new metrics such as ecosystem completeness, w... » read more

Software Driving More Hardware Designs


The influence of software engineers is growing inside of chip and systems companies, reversing a decades-old trend of matching the software to the fastest or most power-efficient hardware and raising as-yet unanswered questions about what will change in SoC design. The shift is particularly evident in chips developed for high-volume markets such as mobile phones and tablets. It's also happen... » read more

As Moore’s Law Slows, Hedge Your Bets With Design Process Efficiency


Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here's why: There are plenty of ways to eke out more scalability in the semiconductor design process through greater efficiency. SoC design realities make it imperative to re-evaluate mature semiconductor processes for greater efficiencies that yield lower costs, higher... » read more

The Week In Review: Design/IoT


Tools Cadence unveiled Joules, its new RTL power analysis solution. The tool performs design synthesis using a new integrated prototype mode of Cadence's Genus Synthesis product, including physically aware clock tree and datapath buffering, and enabling accurate RTL power estimation. IP Synopsys and ASMedia completed a successful interoperability demonstration of Synopsys' USB 3.1 Devi... » read more

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