Making Cache Coherent SoC Design Easier with Ncore

By Arteris - 28 Aug, 2024 - Comments: 0

As the number and variety of computing elements in SoCs grow, specific application areas require the tight connection of key processing elements through coherency. Ncore Interconnect IP from Arteris makes cache coherent SoC designs easier, saving 100’s of person-years effort per project vs DIY solutions. This white paper discusses the challenges and solutions in designing cache-coherent Sy... » read more

As EDA Processes Becomes More Secure, So Do Chips

By Adam Kovac - 26 Aug, 2024 - Comments: 0

Security is becoming a much bigger concern within chips and electronic systems, but the actual implementation remains something of an afterthought, which limits its effectiveness. There are many pieces to the security puzzle on the chip design side that go well beyond just securing the hardware or the IP. The EDA tools themselves need to be secure, as well, and so does the user data within t... » read more

Focus Shifts To Application-Specific Workloads

By Ann Mutschler - 07 Aug, 2024 - Comments: 0

Experts At The Table: EDA has undergone numerous workflow changes over time. Different skill sets have come into play over the years, and at times this changed the definition of what it means to design at the system level. To work out what this means for designers today, and how it looks going forward, Semiconductor Engineering sat down with Michal Siwinski, chief marketing officer at Arteris; ... » read more

Chip Industry Week in Review

By The SE Staff - 02 Aug, 2024 - Comments: 0

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Floor-Planning Evolves Into The Chiplet Era

By Karen Heyman - 25 Jul, 2024 - Comments: 0

3D-ICs and heterogeneous chiplets will require significant changes in physical layout tools, where the placement of chiplets and routing of signals can have a big impact on overall system performance and reliability. EDA vendors are well aware of the issues and working on solutions. Top on the list of challenges for 3D-ICs is thermal dissipation. Logic typically generates the most heat, and ... » read more

What’s Next In System-Level Design?

By Ann Mutschler - 25 Jul, 2024 - Comments: 0

Experts At The Table: EDA has undergone numerous workflow changes over time. Different skill sets have come into play over the years, and at times this changed the definition of what it means to design at the system level. Semiconductor Engineering sat down to discuss what this means for designers today, and what the impact will be in the future, with Michal Siwinski, chief marketing officer at... » read more

Optimizing Interconnect Topologies For Automotive ADAS Applications

By Ashley Stevens - 25 Jul, 2024 - Comments: 0

Designing automotive Advanced Driver Assistance Systems (ADAS) applications can be incredibly complex. State-of-the-art ADAS and autonomous driving systems use ‘sensor fusion’ to combine inputs from multiple sources, typically cameras and optionally radar and lidar units to go beyond passive and active safety to automate driving. Vision processing systems combine specialized AI accelerators... » read more

Securing Data In Heterogeneous Designs

By Adam Kovac - 02 Jul, 2024 - Comments: 0

Data security is becoming a bigger concern as chips are disaggregated into chiplets and various third-party IP blocks. There is no single solution that works for all designs, and no single tool or methodology that addresses everything in any design. Data is being transmitted across time zones, political borders, and even across multiple designs. Laws and the need to comply with standards may... » read more

Streamlining SoC Design With Advanced IP And Integration Solutions

By Andy Nightingale - 27 Jun, 2024 - Comments: 0

As system-on-chip (SoC) complexity grows, so does the necessity for products that seamlessly connect IP and streamline integration processes, minimize manual errors, and enhance productivity. The emphasis on physical awareness across solutions significantly reduces the iterative cycles of NoC placement and routing. By ensuring low latency and high efficiency, these advanced integration solution... » read more

Data Coherence Across Silos And Hierarchy

By Brian Bailey - 27 Jun, 2024 - Comments: 0

Shift left has become a rallying cry for the chip design industry, but unless coherent data can flow between the groups being impacted, the value may not be as great as expected. Shift left is a term that encompasses attempts to bring analysis and decision-making forward in the development process. The earlier an issue can be found, the less of a problem it ultimately becomes. But in many ca... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?