Blog Review: Nov. 27


Synopsys’ Brent Gregory is looking at real-world experiments to figure out which EDA software is better. Make sure to check out his stats. Cadence’s Brian Fuller interviews two Samsung engineers in a video about the image technology in smart phone cameras and just how far it’s progressed. Hint: Don’t forget to charge your phone on your next vacation. Mentor’s Colin Walls points ... » read more

Gartner Recommends Network-on-Chip (NoC) Technology For SoC Design


In their latest Hype Cycle for Semiconductors and Electronics Technologies report, Gartner Research has taken the bold step of recommending that all enterprises involved in advanced SoC design should seriously evaluate network-on-chip (NoC) technology based interconnect fabric IP: “The technology has continued to receive a good amount of publicity along with continued adoption by leading S... » read more

Blog Review: Nov. 20


Can you really heat your home office with just four candles? It all depends on where you put those candles, as Mentor’s Robin Bornoff shows in part one of this series. And make sure you check out the video, particularly if you’ve had a tough day. Synopsys’ Karen Bartleson interviews ST’s Oleg Logvinov on camera about the IoT, which may be the biggest change since the Industrial Revol... » read more

The Week in Review: System-Level Design


Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs. Synopsys teamed up with CEVA to improve PPA for CEVA’s... » read more

The Week In Review: System-Level Design


Qualcomm bought some of Arteris’ IP assets and the bulk of its French design team, but Arteris remains a viable company with a NoC product, customers, and an infrastructure. ARM released a study, in conjunction with the Economist Intelligence Unit, that shows 75% of global business leaders are actively researching opportunities on the Internet of Things. The report says the five barriers f... » read more

Arteris Sells Some Of Its IP Assets To Qualcomm


Qualcomm agreed to buy Arteris’ NoC technology IP and hire some of the engineers who built it, but Arteris will continue to service that IP to new and existing customers. Under terms of the agreement, the two companies also have agreed upon a roadmap for future deliverables of the IP as well as an engineering support contract. Arteris retains the source code for the FlexNoC interconnect IP pr... » read more

Blog Review: Oct. 30


Mentor’s Nazita Saye has stumbled on a phone that you can build yourself from various components. When something breaks, you simply change out what’s broken. Wasn’t that the concept behind the original Volkswagen Beetle? Cadence’s Brian Fuller launches into the discussion about 16nm headaches, including finFET parasitics, pin access and wire resistance. Looks like the transition to f... » read more

Uncertainty Increases About What’s Next


Across the semiconductor industry, there is a lot of talk about what’s next. Lithography advances have stalled, NRE and mask costs are rising, and complexity is exploding. But unlike the 1 micron wall, which was supposed to be impenetrable, there is no single issue holding back progress. Instead, there are lots of them, most with pricey workarounds, but which together become more complicat... » read more

There’s A New Paradigm In Town


I recently wrote an article in the October 9th issue of EETimes that appears to have rattled the semiconductor industry a bit. Entitled “Wake Up, Semi Industry: System OEMs Might Not Need You,” the article conveyed the fact that many system-level OEMs now have the capability — and desire — to develop their own application-specific chips. This may be news to many. But a simple review... » read more

Experts At The Table: Who Takes Responsibility?


Semiconductor Engineering sat down with John Koeter, vice president of marketing and AEs for IP and systems at Synopsys; Mike Stellfox, technical leader of the verification solutions architecture team at Cadence; Laurent Moll, CTO at Arteris; Gino Skulick, vice president and general manager of the SDMS business unit at eSilicon; Mike Gianfagna, vice president of corporate marketing at Atrenta; ... » read more

← Older posts Newer posts →