tag: ASE Group

As Chiplets Go Mainstream, Chip Industry Players Collaborate to Overcome New Development Challenges
By Ashley Huang - 16 Feb, 2023 - Comments: 0

The semiconductor industry is building a comprehensive chiplet ecosystem to seize on the advantages of the devices over traditional monolithic system-on-chips (SoCs) such as improved performance, lower power consumption, and greater design flexibility. With heterogeneous integration (HI) presenting significant challenges, collaboration to fulfill the potential of chiplets has become even more i... » read more

Next Generation Chip Embedding Technology For High Efficiency Power Modules and Power SiPs
By ASE - 15 Sep, 2022 - Comments: 0

Cost, performance, and package size are some of the key drivers required in the next generation of package interconnect and package structure evolution. Embedding active die into substrates was mainly driven by package miniaturization for communication handheld devices. However, in the case of power modules, miniaturization is not the only driver that enhances the need for embedded die substrat... » read more

Week in Review: Manufacturing, Test
By Linda Christensen - 03 Jun, 2022 - Comments: 0

Hybrid Bonding & Supercomputers At this week’s ECTC conference, CEA-Leti and Intel presented an “optimized hybrid direct-bonding, self-assembly process," which they claim has the potential to increase alignment accuracy and speed up fab throughput by several thousand dies per hour. The approach uses capillary forces of a water droplet to align dies on a target wafer. “Commercial s... » read more

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last
By ASE - 16 Dec, 2020 - Comments: 0

The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

Momentum Builds For Advanced Packaging
By Mark LaPedus - 17 Sep, 2020 - Comments: 0

The semiconductor industry is stepping up its efforts in advanced packaging, an approach that is becoming more widespread with new and complex chip designs. Foundries, OSATs and others are rolling out the next wave of advanced packaging technologies, such as 2.5D/3D, chiplets and fan-out, and they are developing more exotic packaging technologies that promise to improve performance, reduce p... » read more

New Developments Of Copper Plating Technology For Embedded Power Chip Packages Challenges
By ASE - 21 Nov, 2019 - Comments: 0

Copper plating has been extensively employed in the fabrication of embedded packaging to reach high-density, high-speed, high performance electronic products. With through holes (TH) as well as blind via aspect ratios increase, development of a reliable plating technology is very important. When the depth of through hole was over 200µm, it is difficult to fill without void by using direct curr... » read more

Week In Review: Design, Low Power
By Jesse Allen - 25 Oct, 2019 - Comments: 0

ANSYS will acquire Dynardo, a provider of simulation process integration and design optimization (PIDO) technology. Dynardo's tools include algorithms for optimization, uncertainty quantification, robustness, scenario variation, sensitivity analysis, simulation workflow building and data mining. Based in Weimar, Germany, Dynardo was founded in 2001 and has been an ANSYS software partner; the ac... » read more

Testing Millimeter Wave for 5G
By Susan Rambo - 05 Nov, 2018 - Comments: 0

By Susan Rambo and Ed Sperling The telecommunications world is hurtling toward 5G, but there is no consistency about how this next-gen wireless technology will be rolled out across various regions and plenty of unknowns about how it will be tested and how reliable it will be initially. A fair amount of confusion exists around what 5G constitutes in the first place. There is sub-6GHz 5G, w... » read more

In Case You Missed It
By Mike Gianfagna - 25 Jan, 2018 - Comments: 0

We recently held two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic p... » read more

What’s Next?
By Mike Gianfagna - 21 Dec, 2017 - Comments: 0

We just concluded two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic ... » read more

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