Fan-Out Packaging Gets Competitive

By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 05 Aug, 2022 - Comments: 0

Pervasive computing, connectivity Semtech Corporation announced that it will acquire Sierra Wireless, an IoT services company. The acquisition will combine Semtech’s LoRa end nodes and cloud service with Sierra Wireless’ cellular capabilities. Telit will incorporate Thales’s cellular IoT products business under a new name Telit Cinterion, led by Telit. Telit Cinterion will be Californ... » read more

Scaling, Advanced Packaging, Or Both

By Ed Sperling - 01 Aug, 2022 - Comments: 0

Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

Week In Review: Manufacturing, Test

By Karen Heyman - 29 Jul, 2022 - Comments: 1

The U.S. Congress approved the CHIPS Act, a mammoth bipartisan achievement the New York Times called “the most significant government intervention in industrial policy in decades.” As passed, the full package — now called the Chips and Science Act — contains $52 billion in direct assistance for the semiconductor industry, along with $24 billion in tax incentives. In addition, the bill c... » read more

Keeping IC Packages Cool

By Laura Peters and Karen Heyman - 07 Jun, 2022 - Comments: 0

Placing multiple chips into a package side-by-side can alleviate thermal issues, but as companies dive further into die stacking and denser packaging to boost performance and reduce power, they are wrestling with a whole new set of heat-related issues. The shift to advanced packaging enables chipmakers to meet demands for increasing bandwidth, clock speeds, and power density for high perform... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 03 Jun, 2022 - Comments: 0

Automotive, mobility Cruise, General Motors’ self-driving car company, obtained a permit to charge for rides in San Francisco, according to a story in Reuters. The California Public Utilities Commission, the regulatory board that can approve permits, voted 4-0 to issue “the first Phase I Driverless Autonomous Vehicle (AV) Passenger Service Deployment permit in California to Cruise LLC to a... » read more

Standardizing Chiplet Interconnects

By John Koon - 23 May, 2022 - Comments: 0

The chip industry is making progress on standardizing the infrastructure for chiplets, setting the stage for faster and more predictable integration of different functions and features from different vendors. The ability to choose from a menu of small, highly specialized chips, and to mix and match them for specific applications and use cases, has been on the horizon for more than a decade. ... » read more

Paving The Way To Chiplets

By Mark LaPedus - 25 Apr, 2022 - Comments: 2

The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

Chiplets Enter The Supercomputer Race

By Mark LaPedus - 17 Mar, 2022 - Comments: 0

Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 04 Mar, 2022 - Comments: 0

Packaging ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC have announced the formation of a consortium that will establish a die-to-die interconnect standard and foster an open chiplet ecosystem. The founding companies also ratified the UCIe specification, an open industry standard developed to establish a standard interconnect at the package level. The UCIe 1.0 s... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: ASE

Fan-Out Packaging Gets Competitive

Week In Review: Auto, Security, Pervasive Computing

Scaling, Advanced Packaging, Or Both

Week In Review: Manufacturing, Test

Keeping IC Packages Cool

Week In Review: Auto, Security, Pervasive Computing

Standardizing Chiplet Interconnects

Paving The Way To Chiplets

Chiplets Enter The Supercomputer Race

Week In Review: Manufacturing, Test

Trending Articles

Baby Steps Toward 3D DRAM

What’s Next For Through-Silicon Vias

Chip Industry Week in Review

Strain, Stress In Advanced Packages Drives New Design Approaches

Navigating Increased Complexity In Advanced Packaging

Knowledge Centers
Entities, people and technologies explored