Chip Industry Earnings: A Mixed Bag


Editor's Note: Updated the week of Oct. 31 and Nov. 7 for additional earnings releases. Although most companies reported revenue growth, this latest round of chip industry earnings releases reflected a few major themes: Lower future quarter guidance to varying degrees, due to the recent U.S. export restrictions related to China; Negative impact of the inflationary environment on corn... » read more

SiPs: The Best Things in Small Packages


System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes. SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical p... » read more

Week In Review: Manufacturing, Test


Highlights from ITC The hot topic at this week’s International Test Conference (ITC) was tackling silent data corruption, with panel discussions, papers, and Google’s Parthasarathy Ranganathan’s keynote address all emphasizing the urgency of the issue. In the past two years Meta, Google, and Microsoft have reported on silent errors, errors not detected at test, which are adversely impact... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Renesas announced its integrated development environment (IDE), which car companies can use to develop automotive software for electronic control units (ECUs) with multiple devices, but for which the hardware has not been specified yet. The IDE has co-simulation, debug and trace, high-speed simulation and distributed processing software over multiple SoCs and MCUs. The first develop... » read more

Week In Review: Manufacturing, Test


On Sunday, a 6.8-magnitude earthquake struck the southeast region of Taiwan, causing devastation. TSMC officials reported “no known significant impact for now.” Market research firm TrendForce arrived at a similar conclusion based on its analysis of individual fabs. The Biden administration announced appointment of the leadership team charged with implementing the US CHIPS and Science Ac... » read more

Improving Redistribution Layers for Fan-out Packages And SiPs


Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

Week In Review: Manufacturing, Test


Some funding details are now available for the CHIPS Act in the U.S. The Biden Administration plans to spend the money in the following ways: $28 billion to establish domestic production of leading-edge logic and memory chips through grants, subsidized loans or loan guarantees; $10 billion to increase production of current-generation semiconductors and chips, and $11 billion for rese... » read more

Fan-Out Packaging Gets Competitive


Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Week In Review: Auto, Security, Pervasive Computing


Pervasive computing, connectivity Semtech Corporation announced that it will acquire Sierra Wireless, an IoT services company. The acquisition will combine Semtech’s LoRa end nodes and cloud service with Sierra Wireless’ cellular capabilities. Telit will incorporate Thales’s cellular IoT products business under a new name Telit Cinterion, led by Telit. Telit Cinterion will be Californ... » read more

Scaling, Advanced Packaging, Or Both


Chipmakers are facing a growing number of challenges and tradeoffs at the leading edge, where the cost of process shrinks is already exorbitant and rising. While it's theoretically possible to scale digital logic to 10 angstroms (1nm) and below, the likelihood of a planar SoC being developed at that nodes appears increasingly unlikely. This is hardly shocking in an industry that has heard pr... » read more

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