tag: ASIC

Talking The Talk On Training
By Mike Gianfagna - 28 Sep, 2017 - Comments: 1

In my prior post, I discussed the value of good design flow training. A properly executed program can turn average engineers into above average problem solvers with the right tools and techniques. We got to thinking about this opportunity quite seriously at eSilicon. Is there a way to develop a focused, intense training program to create a new “army” of elite designers? In short, we thin... » read more

The Secret Life Of Accelerators
By Ed Sperling - 27 Jul, 2017 - Comments: 0

Accelerator chips increasingly are providing the performance boost that device scaling once provided, changing basic assumptions about how data moves within an electronic system and where it should be processed. To the outside world, little appears to have changed. But beneath the glossy exterior, and almost always hidden from view, accelerator chips are becoming an integral part of most des... » read more

Re-Using IP In Packaging
By Ed Sperling - 10 Jul, 2017 - Comments: 0

For the past decade, the promise held forth by advanced packaging was that it would allow chipmakers to mix and match analog and digital IP without worrying about the process node at which they were developed or the physical interactions between components. This is a big deal when it comes to analog. Analog IP doesn't benefit from node shrinking the way digital logic does, and in many cases ... » read more

Software Driven Test Of FPGA Prototype
By Krzysztof Szczur - 27 Apr, 2017 - Comments: 0

Most everyone would agree how important FPGA prototyping is to test and validate an IP, sub-system, or a complete SoC design. Before the design is taped-out it can be validated at speeds near real operating conditions with physical peripherals and devices connected to it instead of simulation models. At the same time, these designs are not purely hardware, but these days incorporate a significa... » read more

The Great Machine Learning Race
By Ed Sperling - 03 Apr, 2017 - Comments: 2

Processor makers, tools vendors, and packaging houses are racing to position themselves for a role in machine learning, despite the fact that no one is quite sure which architecture is best for this technology or what ultimately will be successful. Rather than dampen investments, the uncertainty is fueling a frenzy. Money is pouring in from all sides. According to a new Moor Insights report,... » read more

Embedded FPGAs Come Of Age
By Ann Mutschler - 27 Feb, 2017 - Comments: 0

FPGAs increasingly are being viewed as a critical component in heterogeneous designs, ratcheting up their stature and the amount of attention being given to programmable devices. Once relegated to test chips that ultimately would be replaced by lower-power and higher-performance ASICs if volumes were sufficient, FPGAs have come a long way. Over the last 20 years programmable devices have mov... » read more

Advanced ASICs Are A Team Sport
By Mike Gianfagna - 23 Feb, 2017 - Comments: 0

The recent Super Bowl proved that a team with conviction and focus can do anything. This notion comes in handy when you think about the nearly impossible job of designing and manufacturing an advanced ASIC – in finFET technologies, with an interposer, multiple die, and never-before-proven throughput rates. For these kind of advanced technologies, it does take a village. What works is open, tr... » read more

The Battle To Embed The FPGA
By Brian Bailey - 31 Oct, 2016 - Comments: 1

There have been many attempts to embed an [gettech id="31071" comment="FPGA"] into chips in the past, but the market has failed to materialize—or the solutions have failed to inspire. An early example was [getentity id="22924" comment="Triscend"], founded in 1997 and acquired by [getentity id="22839" e_name="Xilinx"] in 2004. It integrated a CPU—which varied from an [getentity id="22186" co... » read more

Executive Insight: Jack Harding
By Ed Sperling - 03 Aug, 2016 - Comments: 0

[getperson id="11145" comment="Jack Harding"], president and CEO of [getentity id="22242" e_name="eSilicon"], sat down with Semiconductor Engineering to talk about consolidation, business relationships, what it will take to survive in the IoT age, and how to better optimize chips. What follows are excerpts of that conversation. SE: We’ve been looking at consolidation for a while and all th... » read more

CPU, GPU, or FPGA?
By Jeff Dorsch - 16 Jun, 2016 - Comments: 0

Nvidia’s new GeForce GTX 1080 gaming graphics card is a piece of work. Employing the company’s Pascal architecture and featuring chips made with a 16nm [getkc id="185" kc_name="finFET"] process, the GTX 1080’s GP104 graphics processing units boast 7.2 billion transistors, running at 1.6 GHz, and it can be overclocked to 1.733 GHz. The die size is 314 mm², 21% smaller than its GeForce ... » read more

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