tag: ASIC

Have Margins Outlived Their Usefulness?
By Aveek Sarkar - 20 Apr, 2016 - Comments: 0

To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution which we continuously refine over time. Additionally, we have managed the interdependencies between tasks by defining boundaries or margins; these often have been best- and worst-case values used t... » read more

Reprogrammable, Reprogrammable, Reprogrammable
By Aldec - 28 Jan, 2016 - Comments: 0

By Alex Grove I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree ... » read more

C-Based SoC Design Flow And EDA Tools
By Aldec - 21 Dec, 2015 - Comments: 0

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC’s complexity and the timing closure caused by deep submicron technology. To solve these two problems, we propose a C-based SoC design environment t... » read more

An Inside Look At The GlobalFoundries-IBM Deal
By Ed Sperling - 20 Nov, 2014 - Comments: 3

GlobalFoundries' proposed acquisition of IBM Microelectronics is the kind of deal that will have business schools talking for many years to come—a gargantuan combination of expertise and technology, built on the back of high-profile business successes and failures, long-running legal struggles and global politics—with far-reaching implications for all parts of the semiconductor supply chain... » read more

The New ASIC
By Javier DeLaCruz - 25 Jul, 2013 - Comments: 0

By Javier DeLaCruz The current state of the art For years, large ASICs like the ones used in network processing, supercomputing and high-end personal computing have had very interesting similarities. The figure below is a fairly typical floorplan of such an ASIC. After taping out over a dozen of these types of chips a year, it is interesting to see that the interfaces have changed, processo... » read more

End User Report: Reliability
By Ed Sperling - 15 Oct, 2009 - Comments: 0

John Kern, vice president of product operations inside Cisco Systems’ customer value chain management group, sat down with Low-Power Engineering to talk about the company’s internal focus on reliability and what factors are causing the most concern. What follows are excerpts of that conversation. By Ed Sperling LPE: How does Cisco gauge reliability? John Kern: The bulk of our re... » read more

Feel The (Low) Power
By Ed Sperling - 17 Sep, 2009 - Comments: 0

By Clive (Max) Maxfield When I designed my first ASIC way back in the mists of time (circa 1980), its power consumption was the last thing on my mind. You have to remember that we're talking about a device containing only about 2,000 equivalent gates implemented in a 5 micron technology. Also, I was designing this little scamp as a gate-register-level schematic using pencil and paper (I pr... » read more

SOI Goes Mainstream
By Ed Sperling - 20 Nov, 2008 - Comments: 0

By Ed Sperling The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips. For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, ... » read more

Special Report: Semiconductor Road Map Survey
By Ed Sperling - 06 Nov, 2008 - Comments: 0

By Ed Sperling The upcoming semiconductor industry road map, which sets up the industry’s strategy and identifies trends for the next 15 years, is filled with three very interesting shifts and gaps. The road map, which will be formally unveiled next month, consists of findings gleaned from all the top chip companies. Juan-Antonio Carballo, a partner at IBM Venture Capital Group who spea... » read more

Multicore Programming: The Next Frontier?
By Ed Sperling - 22 Oct, 2008 - Comments: 0

By Ed Sperling From a distance it looks like a game of hot potato. But this version is played by hardware and software engineers, who normally don’t have much to do with each other. The hardware engineers say you can’t get any more performance out of a single core on a chip without cooking it, so they’ve added more cores and tossed the problem over the wall to the software e... » read more

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