The New ASIC


By Javier DeLaCruz The current state of the art For years, large ASICs like the ones used in network processing, supercomputing and high-end personal computing have had very interesting similarities. The figure below is a fairly typical floorplan of such an ASIC. After taping out over a dozen of these types of chips a year, it is interesting to see that the interfaces have changed, processo... » read more

End User Report: Reliability


John Kern, vice president of product operations inside Cisco Systems’ customer value chain management group, sat down with Low-Power Engineering to talk about the company’s internal focus on reliability and what factors are causing the most concern. What follows are excerpts of that conversation. By Ed Sperling LPE: How does Cisco gauge reliability? John Kern: The bulk of our re... » read more

Feel The (Low) Power


By Clive (Max) Maxfield When I designed my first ASIC way back in the mists of time (circa 1980), its power consumption was the last thing on my mind. You have to remember that we're talking about a device containing only about 2,000 equivalent gates implemented in a 5 micron technology. Also, I was designing this little scamp as a gate-register-level schematic using pencil and paper (I pr... » read more

SOI Goes Mainstream


By Ed Sperling The crossover for system on insulator (SOI) versus bulk CMOS was supposed to happen at the 22nm, but that was before software developers ran into problems programming multicore chips. For years, SOI was considered the high-performance cousin of CMOS—more expensive, more difficult to manufacture and unnecessary for most applications. It is the heart of the Cell processor, ... » read more

Special Report: Semiconductor Road Map Survey


By Ed Sperling The upcoming semiconductor industry road map, which sets up the industry’s strategy and identifies trends for the next 15 years, is filled with three very interesting shifts and gaps. The road map, which will be formally unveiled next month, consists of findings gleaned from all the top chip companies. Juan-Antonio Carballo, a partner at IBM Venture Capital Group who spea... » read more

Multicore Programming: The Next Frontier?


By Ed Sperling From a distance it looks like a game of hot potato. But this version is played by hardware and software engineers, who normally don’t have much to do with each other. The hardware engineers say you can’t get any more performance out of a single core on a chip without cooking it, so they’ve added more cores and tossed the problem over the wall to the software e... » read more

Verifying ASICs with FPGA Arrays


[youtube vid=pPNvvbCIzO4] » read more

Quality time?


By Ed Sperling System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional design and verification tools and methodology manager at Freescale; Kelly Larson, design verification engineering manager at MediaTek Wireless; Adnan Hamid, CEO of Breker, and ... » read more

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