Making Heterogeneous Integration More Predictable


Experts at the Table: Semiconductor Engineering sat down to discuss problems and potential solutions in heterogeneous integration with Dick Otte, president and CEO of Promex Industries; Mike Kelly, vice president of chiplets/FCBGA integration at Amkor Technology; Shekhar Kapoor, senior director of product management at Synopsys; John Park, product management group director in Cadence's Custom I... » read more

Tradeoffs In DSP Design


More intelligence is now required in the front-, mid-, and back-haul for 5G/6G communication, requiring a mix of high performance, low power, and enough flexibility to accommodate constantly changing protocols and algorithms. One solution to these conflicting goals involves reconfigurable DSPs, in which the processing element is hardwired like an ASIC but still configurable for a variety of app... » read more

Complex Tradeoffs In Inferencing Chips


Designing AI/ML inferencing chips is emerging as a huge challenge due to the variety of applications and the highly specific power and performance needs for each of them. Put simply, one size does not fit all, and not all applications can afford a custom design. For example, in retail store tracking, it's acceptable to have a 5% or 10% margin of error for customers passing by a certain aisle... » read more

Put A Data Center In Your Phone!


Datacenters heavily leverage FPGAs for AI acceleration. Why not do the same for low power edge applications with embedded FPGA (eFPGA)? It’s common knowledge for anyone connected to the cloud computing industry that data centers heavily rely on FPGAs for programmable accelerators enabling high performance computing for AI training and inferencing. These heterogeneous computing solution... » read more

AI ASICs Will Become Increasingly Application-Specific


Back in 2017, I blogged about AI ASICs being not exactly ASICs. One of the primary reasons for not calling AI acceleration chips ASIC is because historically ASIC or Application Specific Integrated Circuit has referred to a fixed hardware block with limited programmability. AI ASICs on the other hand offer significant programming via frameworks such as Tensorflow and the point was that they are... » read more

Power Methodology For Estimation And Optimization In The ASIC/SoC Flow


In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible... » read more

Bespoke Silicon Redefines Custom ASICs


Semiconductor Engineering sat down to discuss bespoke silicon and what's driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens... » read more

Toward Democratized IC Design And Customized Computing


Integrated circuit (IC) design is often considered a “black art,” restricted to only those with advanced degrees or years of training in electrical engineering. Given that the semiconductor industry is struggling to expand its workforce, IC design must be rendered more accessible. The benefit of customized computing General-purpose computers are widely used, but their performance improv... » read more

How Inferencing Differs From Training in Machine Learning Applications


Machine learning (ML)-based approaches to system development employ a fundamentally different style of programming than historically used in computer science. This approach uses example data to train a model to enable the machine to learn how to perform a task. ML training is highly iterative with each new piece of training data generating trillions of operations. The iterative nature of the tr... » read more

New Approaches For Processor Architectures


Processor vendors are starting to emphasize microarchitectural improvements and data movement over process node scaling, setting the stage for much bigger performance gains in devices that narrowly target what end users are trying to accomplish. The changes are a recognition that domain specificity, and the ability to adjust or adapt designs to unique workloads, are now the best way to impro... » read more

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