tag: ATE

Device Validation: The Ultimate Test Frontier
By Dave Armstrong - 11 Apr, 2023 - Comments: 0

This article is a condensed version of an article that appeared in the November/December 2022 issue of Chip Scale Review. Adapted with permission. Read the original article at https://chipscalereview.com/wp-content/uploads/flipbook/30/book.html, p. 26. In the early days of space exploration, spacecraft were manned by small teams of astronauts, most of whom were experienced test pilots who ... » read more

Test Challenges Mount As Demands For Reliability Increase
By Anne Meixner - 07 Mar, 2023 - Comments: 0

An emphasis of improving semiconductor quality is beginning to spread well beyond just data centers and automotive applications, where ICs play a role in mission- and safety-critical applications. But this focus on improved reliability is ratcheting up pressure throughout the test community, from lab to fab and into the field, in products where transistor density continues to grow — and wh... » read more

Hunting For Hardware-Related Errors In Data Centers
By Anne Meixner - 07 Feb, 2023 - Comments: 2

The semiconductor industry is urgently pursuing design, monitoring, and testing strategies to help identify and eliminate hardware defects that can cause catastrophic errors. Corrupt execution errors, also known as silent data errors, cannot be fully isolated at test — even with system-level testing — because they occur only under specific conditions. To sort out the environmental condit... » read more

Engineering Test Station Facilitates Post-Silicon Validation
By Adir Zonta - 07 Feb, 2023 - Comments: 0

The semiconductor market is evolving, with devices becoming more complex as chip designers add cores and pursue 2.5D and 3D integration strategies. This complexity presents challenges extending from design and simulation through system-level test (SLT), where a device is exercised in mission mode, booting up an operating system and running end-user code, for example. These challenges arise f... » read more

Scan Pattern Portability From PSV To ATE To SLT To IST
By Ash Patel - 30 Jan, 2023 - Comments: 0

By Ash Patel and Karthik Natarajan Chip testing has become increasingly complex due to the number of variables impacting designs – from design size and complexity, to high transistor counts on advanced technology nodes, to 2.5D/3D packaging, to manufacturing variability. All of these combine to make testing today's chips and packages more complicated than ever before. The number of test pa... » read more

Emerging Technologies Are Driving System Level Test Adoption
By Natalian Z. Der - 10 Jan, 2023 - Comments: 0

With the size of semiconductor transistors decreasing and chip complexity increasing exponentially, semiconductor test has become essential to ensuring that only high-quality products go to market. With the introduction of more rigorous acceptable quality level (AQL) certifications, test methods must constantly evolve to meet these standards, and system level test (SLT) and traditional test... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures
By Zhenhua Chen - 06 Dec, 2022 - Comments: 0

This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

Simplifying The Path From Design To Test
By Richard Fanning - 08 Nov, 2022 - Comments: 0

By Richard Fanning and John Rowe Getting an integrated circuit (IC) from design to test is an arduous process that encompasses a number of steps, including: Design for Test (DFT): processes that ensure the chip is designed in such a way that it can be tested Development: the development of automated test programs (ATPs) Bench: evaluating the device at the bench to ensure the desig... » read more

Test Connections Clean Up With Real-Time Maintenance
By Anne Meixner - 08 Nov, 2022 - Comments: 0

Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

Yield Is Top Issue For MicroLEDs
By Laura Peters - 11 Oct, 2022 - Comments: 0

MicroLED display makers are marching toward commercialization, with products such as Samsung’s The Wall TV and Apple’s smart watch expected to be in volume production next year or in 2024. These tiny illuminators are the hot new technology in the display world, enabling higher pixel density, better contrast, lower power consumption, and higher luminance in direct sunlight — while consu... » read more

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