tag: ATE

The Good And Bad Of Chiplets
By Mark LaPedus - 27 May, 2020 - Comments: 1

The chiplet model continues to gain traction in the market, but there are still some challenges to enable broader support for the technology. AMD, Intel, TSMC, Marvell and a few others have developed or demonstrated devices using chiplets, which is an alternative way to develop an advanced design. Beyond that, however, the adoption of chiplets is limited in the industry due to ecosystem issu... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 07 Feb, 2020 - Comments: 0

Fab tools Citing the outbreak of the coronavirus in China, SEMI has postponed Semicon/FPD China 2020 and related events originally scheduled for March 18-20, 2020. For the same reason, SEMI will no longer host Semicon Korea 2020 in Seoul, South Korea, February 5-7, as originally scheduled. ------------------------------- Veeco has introduced the new Lumina Metal Organic Chemical Vapor De... » read more

A Breakthrough In Silicon Bring-Up
By Matthew Knowles - 12 Nov, 2019 - Comments: 1

The current semiconductor market is seeing increasingly complex silicon devices for applications like 5G wireless communications, autonomous driving, and artificial intelligence. One of the ways designers are working to control design time and cost is through the adoption of IJTAG (IEEE 1687) for a plug-and-play style IP integration during design. The benefits of using IJTAG are still emerging,... » read more

Simplifying Silicon Bring-Up And Debug On ATE equipment With ATE-Connect
By Mentor, a Siemens Business - 11 Nov, 2019 - Comments: 0

The silicon bring-up process is ripe for improvement. Tessent SiliconInsight with ATE-Connect technology eliminates communication barriers between proprietary tester-specific software and DFT platforms, which accelerates debug of IJTAG devices, speeds product ramps, and reduces time-to-market for products in 5G wireless communications, autonomous driving, and artificial intelligence. Read mo... » read more

How 5G Affects Test
By Ed Sperling - 11 Nov, 2019 - Comments: 0

David Hall, head of semiconductor marketing at National Instruments, talks with Semiconductor Engineering about architectural changes to infrastructure due to the rollout of 5G and how the move from macrocells to small cells is changing test requirements.         Subscribe to Semiconductor Engineering's YouTube Channel here » read more

Silicon Photonics Begins To Make Inroads
By Kevin Fogarty and Ed Sperling - 09 Jul, 2019 - Comments: 1

Integrating photons and electrons on the same die is still a long way off, but advances in packaging and improvements in silicon photonics are making it possible to use optical communication for a variety of new applications. Utilizing light-based communication between chips, or in self-contained modules, ultimately could have a big impact on chip design. Photons moving through waveguides ar... » read more

Power, Reliability And Security In Packaging
By Ed Sperling - 19 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; and Tien Shiah, senior manager for memory at Samsun... » read more

Gaps Emerge In Automotive Test
By Ed Sperling - 07 May, 2019 - Comments: 1

Demands by automakers for zero defects over 18 years are colliding with real-world limitations of testing complex circuitry and interactions, and they are exposing a fundamental disconnect between mechanical and electronic expectations that could be very expensive to fix. This is especially apparent at leading-edge nodes, where much of the logic is being developed for AI systems and image se... » read more

How To Manage DFT For AI Chips
By Rahul Singhal - 09 Apr, 2019 - Comments: 0

Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and Mythic are ASICs based on the novel, massively parallel architectures that maximize data processing capabilities for AI workloads. Others, like Intel, Nvidia, and AMD, are optimizing existing archite... » read more

Anticipating And Addressing 5G Testing Challenges
By Judy Davies - 13 Feb, 2019 - Comments: 0

It’s no surprise that each new generation of ICs raises new sets of challenges in device testing. Changes in pin counts, data-transfer rates and interface protocols present different requirements. With the coming fifth generation (5G) of semiconductor technology, producers of automatic test equipment (ATE) must develop new test solutions with advanced capabilities on several fronts. Perhap... » read more

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