Silicon Photonics Begins To Make Inroads

Maturing processes and new application areas open doors for extremely fast, low-power applications.


Integrating photons and electrons on the same die is still a long way off, but advances in packaging and improvements in silicon photonics are making it possible to use optical communication for a variety of new applications.

Utilizing light-based communication between chips, or in self-contained modules, ultimately could have a big impact on chip design. Photons moving through waveguides are much faster than electrons in copper wire, and it takes far less power to drive optical signals than electrical signals. In addition, there is literally an entire spectrum of options available using light, most with negligible heat dissipation. So far, this remains a largely untapped option in semiconductor design, but that is beginning to change as manufacturing processes and packaging begin to mature.

“There’s a huge development effort, and there are now many tools available on the packaging and foundry side,” said Erik Rasmussen, an analog ASIC designer at Delta Microelectronics. “There are different foundries that provide different diodes for different wavelengths. You can get them optimized for all kinds of things. So now we have a full toolbox, which means you can play around with this for much lower cost. All the development for mechanics and packaging and process are in place. Most things are in place. So now we have a huge toolbox and we can start using to do interesting applications.”

Those applications range from microphones to medical devices, where reflected light is being used to measure vibration or temperature variation. In an optical microphone, for example, an optical laser beams light onto a reflective membrane. As sound waves hit that membrane, the reflected light can be measured and converted into an audio signal. What makes this particularly attractive is the microphone head and the electronics can be separated, limiting various types of interference, and the optical signals are unaffected by magnetic fields. While this works in a typical microphone, it also opens the door to using light for magnetic resonance imaging (MRI), because the signals are unaffected by electromagnetic interference.

“When you have normal image sensors, you have millions of pixels,” Rasmussen said. “But for a dedicated task, that may not be necessary. As a result you can dramatically reduce the power. Maybe you only need 64 pixels. If you think about medical applications, how much do you need to detect the shape of a very small particle? That’s what we’re looking into. How do you take advantage of this in a way that uses very low energy.”

Moving large amounts of data
This is an entirely different approach than using light to move massive amounts of data between server racks and external storage, or between chips within a package. But it does show just how far optical communication has progressed. Until a couple years ago, there was no standard way of even connecting an optical signal to the die, or for fiberoptic connections to reach inside data center server rack. That has changed significantly, and pushing optical communication down to the device level is now possible.

In-package photonic modules would be the next big step in the evolution of electro-optical integration, as well a major volume driver for this technology, according to Gilles Lamant, distinguished engineer at Cadence. Circuit-board-mounted packages don’t approach full electro-optical integration, but they are an advancement beyond top-of-rack connections or the optical ports attached to chassis-server front-plates, which are the current standard of electro-optical connections.

The eventual goal is to put the electronic IC, photonic IC (PIC), the CMOS-based driver for the transceiver/receiver and even the laser all together on the same chip, which at this point is a long way from reality.

“That is not possible at this time,” said Norman Chang, chief technologist for the semiconductor business unit at ANSYS. “Putting everything together is a long-term goal of the industry. Right now the closest we can come is to put all these components nearby in a 3D-IC configuration.”

In fact, just being able to attach the package containing the photonic interface to a substrate inside the rack is a big step beyond the photonic connections on the outside of a server chassis, Lamant said. “Co-packaged optics is really what is happening right now. We’re not as close to the processor and memory as we could be, but [the closest connecting point is] no longer at the top of the rack. Companies like Rockley are demonstrating devices where they replace the long ridge copper track that used to be on the board in the blade with very short-reach electrical links, and what comes out is a ribbon of fiber and all that are in the package.”

Putting the connector inside, on the circuit board of rack-mounted switches or servers, doesn’t deliver the goal of real silicon/photonic integration that chip designers and researchers have been working toward for decades. But it does mean fiber could replace some copper in board-level I/O channels, and make fiber-to-the-server connections easier to manage, Lamant said.

The ability to run fiber to the server would be popular in data centers, which are drowning in rising tide of user and machine-produced data. And that would push photonic chip makers out of the comparatively low-volume-sales world of the telecom and optical-networking market and into the data center server market, which requires high-volume production and the kind of design and planning efficiency that requires.

That also begins to add economies of scale into photonics, driving down the cost and making it attractive for EDA and equipment companies to commit resources to this sector.

“The industry roadmap shows optics or silicon photonics,” said Eelco Bergman, senior director of sales and business development at ASE. “There is fiber through to the final connection in the switch through the PCB, but long-term you want to move optics onto the switch on BGA. If you mount it directly on the BGA it gets smaller in form factor, and you can connect it on top of another package. That makes routing simpler. You don’t have to deal with differential pairs, but you do have the complexity of electrical routing out to the optical engines. Longer-term, a silicon interposer actually can become a photonics IC. Today, it serves as a base platform for a photonics IC. It’s a passive part used for routing.”

EDA tools
Still, none of this was possible several years ago.

“In a lot of ways we’re sitting here in almost 2020 and what we’re dealing with is almost like CMOS design testing from the early 1980s,” said Tom Daspit, product marketing manager of the custom IC division of Mentor, a Siemens Business. “There is not a set of established best practices to follow, and everyone had a different idea of how to do things, so it’s really the Wild West—there’s no single guiding principle to follow. We know a lot about the process, but there are no abstractions. Tools that can automate a lot of the process for the user are just not there yet. And you’re dealing with a foundry that is used to making transistors. You’re coming to them and saying, ‘I need these devices dealing with light and with some electrical connections, as well.’ They’re not prepared.”

There has been some progress on this front, though. “There is a feeling that the industry got into this a little early several years ago” said Duane Boning, professor of electrical engineering and computer science at MIT. “But now you see companies like Ayar Labs working with Intel and pushing silicon photonics in CMOS. That’s a mature platform, and it’s easier to integrate photonics with digital. But one thing we need to more of is design for manufacturing.”

Optical networking was focused exclusively in the telecom market for so long that the established design and manufacturing best practices are all geared toward volumes that are low compared with data-center market norms. The verification process also leaves much to chance.

“In photonics, we’ve seen for a long time that people just adopted a correct-by-construction approach where they design something, send it out, get the samples back and find it doesn’t work, so they figure out what’s wrong and send it out to manufacturing and go around like that until you get something that works the way it should,” said John Ferguson, director of marketing for Calibre DRC applications at Mentor. “Often the designers are Ph.Ds who come from the assumption that they know how to design photonics because they’ve been doing it for 10 years. But sometimes you want to remind them that they’re used to designing things with tens of photonic components, and you want to get it to the point of having thousands or possibly millions of components and manufacture a lot more of them a lot faster than they have been doing.”

The number of tools available for PIC design is probably lower than the number available for electronics, but that’s not the important thing about them, said Mitch Heins, business development manager at Synopsys. “The next big thing is to integrate them, so what you want to do is figure out how do we weave this stuff into a co-design environment. The cost of a PIC right now can be 80% to 90% of the package. Electronics was like that once, when everything was a component, before they were all integrated into circuit boards. We have three decades of experience designing electronics that went into improving their efficiency and bringing down costs. It will work the same way with PICs. We’ll integrate the pieces and that will bring the price down.”

Silicon photonic development hasn’t just been held back by a lack of tools, though. The scale and physics of optical circuitry is so different from electronic, it is difficult to even attach them to the same surface, let alone get them working together efficiently.

“Photonic elements are huge, for one thing—microns, not nanometers,” Daspit said. “That’s one reason this has taken so long. The initial thinking was that we could take a silicon process already used for electronics manufacturing and migrate it over to use with photonics and everything would be great. It’s not the only reason, but photonic elements are huge and you don’t want to spend as much as it would cost for a 10nm module for something that takes up a giant amount of space and only includes a few elements. The other aspect is that we’ve had a long time in electronics design to learn from our mistakes. They haven’t really had time for that in photonics yet.”

It also requires a new way of thinking about chip design.

“Everything on the electronics side is rectilinear, but photonics are curved, which doesn’t bode well if you just take a design and try to render it into GDSII, which doesn’t support curves,” Ferguson said. “Everything is correctable, but you need different tools or different skills, and right now even the foundry might not have the skill set or specific tools to solve an issue. It takes time to adapt the tools and for best practices to be developed and propagated. People are working on it, but it’s not there yet.”

Assembly and packaging is different, too. Aligning a fiber connection to the edge of a chip to funnel down to the wave guide means matching one element that might be 200 nm with another that can be measured only in microns, but the alignment of elements has to be perfect in three dimensions—much more precisely than an electric connection over copper, or light can not pass through.

“Most of that is using active alignment, so a human is involved in physically moving things around,” Heins said. “That works fine in an R&D lab, but in production with any volume you can’t afford to do that.”

Curving components and differences in design-rule checking for photonic layout-vs-schematic (LVS) testing makes verification more complex. The lack of specific guides, tools and specifications for photonic components also makes circuit simulation more difficult by returning false violations for elements that might cause a short in electronic designs but are perfectly valid for photonics, according to an analysis in Semiconductor Engineering by Omar El-Sewefy, DRC Technical Lead in Mentor’s Design to Silicon Division.

Fig. 1: Comparison between LVS techniques for silicon photonics shows superior coverage of shape-matching LVS. Source: Mentor, a Siemens Business

Test and other challenges
Test options, meanwhile, are few enough that many companies end up building their own automatic test equipment for photonics because traditional standalone ATE doesn’t take the oddities of photonic design into account, according to David Hall, principal marketing manager at National Instruments.

“One of the challenges we see is that, because of these odd configurations, electronic and photonic devices that don’t integrate easily,” Hall said. “You can’t just place a photonic transceiver in a typical socket the way you can with most package parts. The instrument interfaces are very different than, say, a power-management IP or a DAC and ADC, where instead of just supplying voltage and current, you’re supplying light, too. Very little test equipment is set up to handle that. “

Thermal sensitivity is another issue. While the light generates little or no heat, heat dissipation from other circuits and from the laser itself can cause problems.

“You have a big, hot ASIC sitting right next to the fiber, which can distort the wavelengths so the whole spectrum will shift—and the laser is another big, hot element,” Heins said. “You have to know you can keep the fiber at the same temperature even when it’s not being overheated by the ASIC or the laser, but you’ll sometimes want to put in itty bitty heaters too—just resistors, nothing big, to make sure you can control the temp, not just keep it from overheating.”

The whole package—including the laser, the wave guide, the electronic IC, the PIC and CMOS driver are individually and collectively so sensitive to changes in temperature that the package design should include controls that would minimize the difference between a plug on the outside of the rack and a mount inside on the circuit board, ANSYS’ Chang said.

“Inside the server box, with the operation of the fan and the heat sink, is just the temperature outside the silicon photonics module,” Chang said. “As long as you have good control inside the package, that’s what we look for. There is inductance, crosstalk, signal integrity and power integrity, the impact of high frequency components, thermal and mechanical stress. But if you can’t control the thermal gradient inside the package, you can’t control the performance of silicon photonics. That’s the make-or-break issue for 3D-IC phase for silicon photonics.”

There are other issues, as well. Cost, for instance is a big concern in mass production implementations, but it is less of an issue in some markets where that cost can be amortized across a system.

“I’m looking at a project now where X-Fab has some photodiodes in their library,” said Delta’s Rasmussen. “We certainly can use a lot of things that haven’t been available before. Especially on the packaging side, there are some very good packaging houses that can do some very interesting stuff. It’s customized, but they’ve done it so many times that it doesn’t cost as much as before, and there is much better control over tolerances.”

That kind of approach is beginning to spread, and market projections reflect these kinds of changes.

“Copper is not finished,” Lamant said. “There are places copper doesn’t work, and is limited, but there are companies making sure you can go up to 50Gbit/sec, but you see a lot of companies that are using it as a kind of Plan B in case Plan A doesn’t work out in time. It is a risk mitigation approach, because copper has a big, stable, mature industry behind it. But they know Plan B won’t last forever.”

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Scott Jordan says:

Great article!

It states correctly, “‘Most of that is using active alignment, so a human is involved in physically moving things around,’ Heins said. ‘That works fine in an R&D lab, but in production with any volume you can’t afford to do that.’”

…Worse, the alignment must be performed multiple times, starting with testing the chips while still on the wafer, and recurring through the packaging process. The alignment must also occur in up to 6 degrees of freedom, not just the 3 noted in the article. For example, photonic devices with more than one input or output (array configurations) require precise rotational alignment around the optical axis. And a chip can have more than one input and output, making global alignment a real challenge.

Fortunately this problem has been solved by fab-class OEM micro-robotic mechanisms with integrated, multi-DOF alignment capability that can perform multiple alignments in parallel. You can see this at work in FormFactor’s Cascade photonics wafer probers, which integrate these high-throughput nanopositioning mechanisms that automatically find and lock-onto the photonic coupling.

Scott Jordan
Head of Photonics
Physik Instrumente (PI)

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