tag: ATPG

Power-Aware Test Vector Porting For Production ATE
By Hari Mani - 12 Nov, 2024 - Comments: 0

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and frequency scaling (DVFS) can adjust to changing conditions and incrementally adjust power and performance on the fly. Power management starts from the lowest hardware level of transistor structures ... » read more

Power-Aware Revolution In Automated Test For ICs
By Gregory Haley - 11 Jun, 2024 - Comments: 0

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip. Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously consider... » read more

Supporting Multiple Time Domains In SoC Production Test
By Hari Mani - 14 May, 2024 - Comments: 0

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for defective wafers and assembled chips is always challenging. Production test engineers constantly struggle to minimize expensive test pattern memory, test each wafer or chip as quickly as possible, and... » read more

AI-Driven Test Optimization Solves Semiconductor Test Costs And Design Schedules
By Sri Ganta - 08 Feb, 2024 - Comments: 0

Artificial Intelligence has become a pervasive technology that is being applied to solve today’s complex problems, especially in the areas involving exponentially large amounts of data, their analysis, and corresponding decision making that are otherwise limited by human abilities. Therefore, complex challenges in semiconductor design, test and manufacturing are a perfect match for AI. The... » read more

Testing ICs Faster, Sooner, And Better
By Laura Peters - 12 Dec, 2023 - Comments: 0

The infrastructure around semiconductor testing is changing as companies build systems capable of managing big data, utilizing real-time data streams and analysis to reduce escape rates on complex IC devices. At the heart of these tooling and operational changes is the need to solve infant mortality issues faster, and to catch latent failures before they become reliability problems in the fi... » read more

New Type Of Hardware Trojans Based On Logic Locking
By Technical Paper Link - 03 Oct, 2023 - Comments: 0

A technical paper titled “Logic Locking based Trojans: A Friend Turns Foe” was published by researchers at University of Maryland and University of Florida. Abstract: "Logic locking and hardware Trojans are two fields in hardware security that have been mostly developed independently from each other. In this paper, we identify the relationship between these two fields. We find that a com... » read more

Reducing Chip Test Costs With AI-Based Pattern Optimization
By Rahul Singhal - 31 Jul, 2023 - Comments: 0

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested. The slower the test throughput, the more automatic test equipment (ATE) is needed to meet production throughput demands. This is a huge issue for chip producers, since high pin counts, blazingly ... » read more

Journey From Cell-Aware To Device-Aware Testing Begins
By Laura Peters - 06 Jun, 2023 - Comments: 0

Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device failures even when test programs achieved 100% fault coverage, it went about addressing this disconnect between the way defects manifest themselves inside devices and the commonly used fault mod... » read more

Pinpointing Timing Delays Can Improve Chip Reliability
By Anne Meixner - 09 May, 2023 - Comments: 0

Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

What Data Center Chipmakers Can Learn From Automotive
By Anne Meixner - 11 Apr, 2023 - Comments: 2

Automotive OEMs are demanding their semiconductor suppliers achieve a nearly unmeasurable target of 10 defective parts per billion (DPPB). Whether this is realistic remains to be seen, but systems companies are looking to emulate that level of quality for their data center SoCs. Building to that quality level is more expensive up front, although ultimately it can save costs versus having to ... » read more

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