tag: ATPG

In-System/In-Field Testing Using High-Quality Deterministic Test Patterns
By Ashrith Harith - 10 Jun, 2025 - Comments: 0

The amount of electronic content in passenger cars is growing rapidly, primarily due to the integration of advanced safety features. The shift towards fully autonomous vehicles, which must comply with stringent safety standards, will further increase the number of electronic components required. Testing efforts must be of exceptional quality. The target test time is often limited to less than 1... » read more

Can Your ATPG Do This? Cut Defects Escaping Detection With ML
By Alex Burlak - 10 Jun, 2025 - Comments: 0

Chipmakers worldwide consider Automatic Test Pattern Generation (ATPG) their go-to method for achieving high test coverage in production. ATPG generates test patterns designed to detect faults in the silicon and ensures they are applied effectively using the chip’s Design-for-Test (DFT) infrastructure. This combination enhances fault detection while optimizing test efficiency. These patter... » read more

A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)
By Technical Paper Link - 31 May, 2025 - Comments: 0

A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

Better ATPG To Minimize Chip Test Time And Cost
By Hari Mani - 08 May, 2025 - Comments: 0

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, simulated, laid out, and checked in about the same time with the same effort, despite the growth in die size and density. One area of particular focus is manufacturing test. Any effort expended to reduce t... » read more

Unlocking The Value Of Yield
By Marc Hutner - 11 Mar, 2025 - Comments: 0

Have you stopped to consider the impact of yield on your overall product cost? Of course you did, when you considered your yield targets and set your product goals. But is it good enough to stop once the goals are achieved, or should you find ways to drive additional value into your organization once production has begun? What is the value of a 1% improvement in product yield? The short answer ... » read more

Power-Aware Test Vector Porting For Production ATE
By Hari Mani - 12 Nov, 2024 - Comments: 0

Power management in contemporary system-on-chip (SoC) designs is almost unimaginably complex. Processors and other chip cores turn on and off as needed. Advanced features such as dynamic voltage and frequency scaling (DVFS) can adjust to changing conditions and incrementally adjust power and performance on the fly. Power management starts from the lowest hardware level of transistor structures ... » read more

Power-Aware Revolution In Automated Test For ICs
By Gregory Haley - 11 Jun, 2024 - Comments: 0

As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip. Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously consider... » read more

Supporting Multiple Time Domains In SoC Production Test
By Hari Mani - 14 May, 2024 - Comments: 0

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for defective wafers and assembled chips is always challenging. Production test engineers constantly struggle to minimize expensive test pattern memory, test each wafer or chip as quickly as possible, and... » read more

AI-Driven Test Optimization Solves Semiconductor Test Costs And Design Schedules
By Sri Ganta - 08 Feb, 2024 - Comments: 0

Artificial Intelligence has become a pervasive technology that is being applied to solve today’s complex problems, especially in the areas involving exponentially large amounts of data, their analysis, and corresponding decision making that are otherwise limited by human abilities. Therefore, complex challenges in semiconductor design, test and manufacturing are a perfect match for AI. The... » read more

Testing ICs Faster, Sooner, And Better
By Laura Peters - 12 Dec, 2023 - Comments: 0

The infrastructure around semiconductor testing is changing as companies build systems capable of managing big data, utilizing real-time data streams and analysis to reduce escape rates on complex IC devices. At the heart of these tooling and operational changes is the need to solve infant mortality issues faster, and to catch latent failures before they become reliability problems in the fi... » read more

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