The X Factor

By Ed Sperling - 30 May, 2013 - Comments: 0

By Ed Sperling The number of unknowns is growing in every segment of SoC design all the way through manufacturing, raising the stakes between reliability and the tradeoffs necessary to meet market windows. Tools are available to deal with some of these unknowns, or X’s, but certainly not all of them. Moreover, no single tool can handle all unknowns, some of which can build upon other unkn... » read more

Power Becomes Bigger Issue In Stacked Die

By Ed Sperling - 10 May, 2013 - Comments: 0

By Ed Sperling Concern over getting the heat out of stacked die is well defined, even if the current raft of existing and proposed solutions ranges from ineffective to exotic and expensive. What is less well understood is how to plan for and manage power inside of stacked die. While power and heat frequently go hand in hand—where there is heat there is almost always power dissipation—t... » read more

What’s Missing In Low-Power Verification

By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Ask two engineers what low-power verification is and you’ll likely get the same checklist that includes confidence in the overall design, good coverage, a long list of corner cases, and other items in a checklist. Ask them how to reach that goal you’ll almost certainly get different answers—or maybe no answers at all. Power has emerged as a ubiquitous concern in design,... » read more

DAC Is Where?

By Atrenta - 09 May, 2013 - Comments: 0

By Mike Gianfagna DAC season is upon us. I gave up counting the number of DACs I’ve attended a long time ago—when I turned 29 for the third time, I believe. This year, DAC is special in a few important ways. First of all, it’s the 50th DAC. Yes, the show has indeed been around that long. It started as a workshop with a bunch of engineers debating algorithms. For an industry that is arg... » read more

Taking Aim At Big Data

By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ed Sperling As the Internet of Things bridges the gap between the mobile and big data worlds, EDA and IP vendors increasingly are looking well beyond their usual boundaries. How successful they are at moving upward into a market that is far less price-sensitive remains to be seen. But from a technology standpoint, at least, the issues encountered by data centers and cloud providers are ... » read more

Design Topology Requires Physical Data

By Ann Mutschler - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

Optimizing IP For Power

By Ed Sperling - 11 Apr, 2013 - Comments: 0

By Ed Sperling As the amount of commercial IP in an SoC increases, the entire bill of materials is coming under increasing scrutiny because of a new concern—power. Commercial IP, after all, is largely a collection of black-box solutions to speed up the time it takes to bring a chip to market, and frequently to improve the quality, but the cumulative impact on the system power budget has neve... » read more

The Power Game

By Ann Mutschler - 11 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Semiconductor engineering teams always have focused on stepping up performance in new designs, but in the mobile, GPU and tablet markets they’re finding that maintaining the balance between higher performance and the same or lower power is increasingly onerous. The reason: Extreme gaming applications can create scenario files that cause dynamic power consumpt... » read more

RTL Restructuring

By Various Writers - 11 Apr, 2013 - Comments: 0

We all know that hierarchy created for logic design must often be adjusted to map to a physical implementation. Logic hierarchy is typically constrained by non-implementation factors, especially organization of teams working on different components and use of legacy or 3rd party IP. Physical hierarchy, on the other hand, must partition the logic to fit detailed implementation tool capacity limi... » read more

Start Early, Cover All The Bases

By Bernard Murphy - 11 Apr, 2013 - Comments: 0

Design for low power always has challenged designers and design tools. You need to have accuracy, because you are estimating implementation-centered parameters, but you need to start early, before implementation, if you are to have any hope of meaningfully reducing power. Sure, you can always play with body-bias, but that is a crude control. Real reductions after architecture always come throug... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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