tag: Atrenta

The Growing Integration Challenge
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling As the number of processors and the amount of memory and IP on a chip continues to skyrocket, so does the challenge for integrating all of this stuff on a single die—or even multiple dies in the same package. There are a number of reasons why it’s getting more difficult to make all of these IP blocks work together. First of all, nothing ever stands still in design. As a r... » read more

Power Impacts On Advanced Node IP
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ann Steffora Mutschler With the move to the 28nm or 20nm process nodes, SoC engineering teams are seeing a significant amount of variations due to manufacturability. To reflect how a design element will be printed on the wafer, foundries offer many libraries with multiple corners for different voltages, timing and temperature, among other things. “At 28nm what we are seeing is a l... » read more

Roundtable: Lower-Power Chips
By Ed Sperling - 08 Nov, 2012 - Comments: 0

Low Power-High Performance Engineering talks about problems in low-power design with Richard Trihy of GlobalFoundries, Leah Clark of Broadcom, Qi Wang of Cadence and Venki Venkatesh of Atrenta. [youtube vid=cD560pgEegk] » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 08 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What are ... » read more

Experts At The Table: The Business Of IP
By Ed Sperling - 26 Oct, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss IP supply chain issues with Jim Hogan, an independent VC; Jack Brown, senior vice president at Sonics; Mike Gianfagna, vice president of marketing at Atrenta; Paul Hollingworth, vice president of strategic accounts at eSilicon, and Warren Savage, CEO of IPextreme. What follows are excerpts of that conversation. LPHP:... » read more

The New Mixed-Signal Flow
By Ed Sperling - 25 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler We are on the cusp of the mixed-signal era. Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, no longer are sufficient. They lead to excess iteration and prolonged design cycle time. Today’s mixed-signal designs require a new approach that enables design teams to be as efficient as possible productivity... » read more

Experts At The Table: The Business Of IP
By Ed Sperling - 19 Oct, 2012 - Comments: 0

Low-Power/High-Performance Engineering sat down to discuss IP supply chain issues with Jim Hogan, an independent VC; Jack Brown, senior vice president at Sonics; Mike Gianfagna, vice president of marketing at Atrenta; Paul Hollingworth, vice president of strategic accounts at eSilicon, and Warren Savage, CEO of IPextreme. What follows are excerpts of that conversation. LPHP: There’s so muc... » read more

Transitioning States
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ann Steffora Mutschler While the concept of finite state machines is mature, understanding their role in design, the transitions between them and how to verify them are fundamental to managing power in today’s large SoCs. In essence, a finite state machine is a set of inputs and outputs and gate bits that describes the operation of the system. “Transitions happen from one state to... » read more

Design For Power
By Ed Sperling - 11 Oct, 2012 - Comments: 0

By Ed Sperling Figuring out a single power budget and mapping out what has become known as holistic power intent for an SoC sounds great on paper, but reality has turned out to be somewhat different. While system architects still call the shots on how a chip is designed, there is a lot more information flowing in all directions further down the design chain these days. Unlike functionality,... » read more

The IP Kit
By Various Writers - 11 Oct, 2012 - Comments: 0

This white paper focuses on how SoC designers and integrators can effectively assess the quality and completeness of soft IP cores. A methodology for accomplishing this goal is presented, and an overview is provided of the Atrenta IP Kit - an application of the SpyGlass platform that implements a soft IP quality qualification methodology. To download this white paper, click here. » read more

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