Tech Talk: Atrenta CTO

By Ed Sperling - 06 Jun, 2011 - Comments: 0

Bernard Murphy talks with System-Level Design about what's changing in the semiconductor design area, how 3D stacking will affect design and what's needed in EDA tools. [youtube vid=kT3vs4sldSk] » read more

Who’s In Control?

By Ed Sperling - 26 May, 2011 - Comments: 0

By Ed Sperling A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there. Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA comp... » read more

EDA…Or Something Else?

By Atrenta - 26 May, 2011 - Comments: 0

The Design Automation Conference is almost here. That major focal point for the EDA industry where we gather to explain the present, predict the future, have a bunch of serious meetings and maybe a little fun, too. Some companies will stage an incremental update of their strategy and others will outline a major new strategy. This year, Atrenta will be talking strategy, with some announcement... » read more

SoC Realization: The Linchpin To Enabling Electronics Innovation

By Various Writers - 11 May, 2011 - Comments: 0

There are significant changes occurring in the electronics industry. The widespread consumerization of electronic devices has permanently changed our lives for the better. The rate at which hand-held, personal electronic products are evolving is staggering by any historical measure. These rapid advances are facilitated by system on chip (SoC) devices, the microelectronic marvels of engineering ... » read more

‘What If’ In 3D

By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling ‘What if’ questions have become standard across multiple pieces of the design chain for any SoC, but the number is multiplying at each new process node. When the industry begins moving to 2.5D and 3D over the next couple years, the number of tradeoffs will likely move from overwhelming to unmanageable. That will set in motion a number of efforts in semiconductor design. ... » read more

EDA’s Big Challenge

By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ann Steffora Mutschler It is not news to anyone that the growth rate of the EDA industry has been less than impressive, to put it politely. Traditional EDA implementation tools have hit commodity status and something’s got to change. Thankfully, there are a host of challenges coming in the form of system-level (and higher) design, not to mention what will be required for true 3D chips. ... » read more

The Multiple Faces Of Virtual Prototyping

By Ann Mutschler - 28 Apr, 2011 - Comments: 0

Virtual prototyping conjures either confusion or relief, so it should come as no surprise that some chip designers are still confused about the different types of prototypes on the market. “Virtual prototyping is going through a change right now,” explained Gary Smith, founder and chief analyst for Gary Smith EDA. “Today, users are using cycle-based tools to prototype sections of their... » read more

Understanding Formal Verification Concepts

By Various Writers - 28 Apr, 2011 - Comments: 0

In today’s complex system on chip (SoC) designs, verification has become a real challenge. Register transfer level (RTL) and gate-level simulations are effectively used for verifying the functional correctness of any design. However, as designs are growing in size as well as functionality, more and more test vectors need to be created and run to get reasonable test coverage. In addition to th... » read more

The Quest For A Better IP Integration Methodology

By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Keeping Up With Complexity

By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

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