The Race To Much More Advanced Packaging

By Mark LaPedus - 23 Jul, 2020 - Comments: 2

Momentum is building for copper hybrid bonding, a technology that could pave the way toward next-generation 2.5D and 3D packages. Foundries, equipment vendors, R&D organizations and others are developing copper hybrid bonding, which is a process that stacks and bonds dies using copper-to-copper interconnects in advanced packages. Still in R&D, hybrid bonding for packaging provides mo... » read more

Advanced Materials For High-Temperature Process Integration

By James Lamb - 16 Jul, 2020 - Comments: 0

From the last several lithography nodes, in the 14 to 10nm range, to the latest nodes, in the 7 to 5nm range, the requirements for patterning and image transfer materials have increased dramatically. One of the key pinch points is the tradeoff between planarization and the high-temperature stability required from carbon films used in patterning and post-patterning process integration. Patter... » read more

The Next Advanced Packages

By Mark LaPedus - 18 Jun, 2020 - Comments: 4

Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

EUV’s Uncertain Future At 3nm And Below

By Mark LaPedus - 21 May, 2020 - Comments: 5

Several foundries have moved extreme ultraviolet (EUV) lithography into production at both 7nm and 5nm, but now the industry is preparing for the next phase of the technology at 3nm and beyond. In R&D, the industry is developing new EUV scanners, masks and resists for the next nodes. 3nm is slated for 2022, followed by 2nm a year or two later. Nonetheless, it will require massive funding... » read more

Super Planarizing Material For Trench And Via Arrays

By Brewer Science - 21 May, 2020 - Comments: 0

As device design scales and becomes more complex, fine control of patterning and transfer steps is integral. Planarization of deep trenches and via arrays has always been a challenge. Aspect ratios continue to increase while critical dimensions shrink, and typical trench fill schemes are no longer able to meet the fill and planarization requirements. Traditional design of spin-on carbon (SOC) m... » read more

Metrology Challenges For Gate-All-Around

By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond

By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

Big Changes In Tiny Interconnects

By Ed Sperling - 16 Apr, 2020 - Comments: 1

One of the fundamental components of a semiconductor, the interconnect, is undergoing radical changes as chips scale below 7nm. Some of the most pronounced shifts are occurring at the lowest metal layers. As more and smaller transistors are packed onto a die, and as more data is processed and moved both on and off a chip or across a package, the materials used to make those interconnects, th... » read more

Improving EUV Process Efficiency

By Mark LaPedus - 19 Mar, 2020 - Comments: 2

The semiconductor industry is rethinking the manufacturing flow for extreme ultraviolet (EUV) lithography in an effort to improve the overall process and reduce waste in the fab. Vendors currently are developing new and potentially breakthrough fab materials and equipment. Those technologies are still in R&D and have yet to be proven. But if they work as planned, they could boost the flo... » read more

Thin Film Characterization For Advanced Patterning

By Brewer Science - 18 Mar, 2020 - Comments: 0

Authors: Zhimin Zhu; Xianggui Ye; Sean Simmons; Catherine Frank; Tim Limmer; James Lamb Brewer Science, Inc. (United States) A variable-angle spectroscopic ellipsometer (VASE) is an essential tool for measuring the thickness of a thin film, as well as its n and k optical parameters. However, for films thinner than 10 nm, precise measurement is very challenging. In this paper, the root cause... » read more

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Knowledge Centers
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