tag: Brewer Science

Defect Reduction At 7/5nm
By Ed Sperling - 12 Jul, 2018 - Comments: 0

Darin Collins, director of metrology at Brewer Science, talks about the cause of defects at advanced nodes and how material purity increasingly plays a role in overall quality and yield. » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 29 Jun, 2018 - Comments: 0

Chipmakers and OEMs Fujitsu Semiconductor and United Microelectronics Corp. (UMC) announced that UMC will acquire all of the shares of Mie Fujitsu Semiconductor Limited (MIFS), a 300mm wafer foundry joint venture between both companies. In addition to the 15.9% of MIFS shares currently owned by UMC, Fujitsu Semiconductor will transfer the remaining 84.1% of its shares in MIFS to UMC, making MI... » read more

Sacrificial Laser Release Materials For RDL-First Fan-Out Packaging
By Brewer Science - 11 Jun, 2018 - Comments: 0

The semiconductor industry is in a new age where device scaling will not continue to provide the cost reductions or performance improvements at a similar rate to past years when Moore’s law was the guiding principle for IC scaling. The cost of scaling below 7 nm nodes is rising substantially and requires significant investment in capital equipment and R&D spending for next-generation lithogra... » read more

The Growing Materials Challenge
By Katherine Derbyshire - 11 Jun, 2018 - Comments: 0

By Katherine Derbyshire & Ed Sperling Materials have emerged as a growing challenge across the semiconductor supply chain, as chips continue to scale, or as they are utilized in new devices such as sensors for AI or machine learning systems. Engineered materials are no longer optional at advanced nodes. They are now a requirement, and the amount of new material content in chips contin... » read more

Temporary Bonding: Enabling the Next Generation of Ultrathin Wafers
By Kim Yess - 11 Jun, 2018 - Comments: 0

Innovative materials are critical for maintaining integrity during advanced semiconductor manufacturing processes. Temporary bonding is being enabled by these new materials and is making a name for itself in the next generation of ultrathin wafer manufacturing. Semiconductor wafers are being forced to become thinner as the push to shrink feature sizes and introduce full-scale 3D integration ... » read more

Surface Modification: Solving Semiconductor Manufacturing Challenges
By Reuben Chacko - 07 May, 2018 - Comments: 0

Process reliability and faster technology deployment are two of the most pressing manufacturing challenges currently facing the semiconductor industry. In a world of ever-evolving technology and innovation, engineers are working to transform materials that don’t possess all the desired functions through a method called “surface modification” – the act of modifying a material’s surface... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 20 Apr, 2018 - Comments: 2

Trade The trade tensions are building between the U.S. and China. In the latest move, the U.S. Department of Commerce has imposed a ban on U.S. companies selling chips to ZTE, a Chinese telecom equipment and mobile phone vendor. The ban has been implemented on ZTE for seven years after the firm “was caught illegally shipping U.S. goods to Iran,” according to a report from Reuters. This ... » read more

Searching For EUV Defects
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production. One lingering issue that is becoming more worrisome is how to find defects caused by [gettech id="31045" comment="EUV"] processes. These processes can cause random variations, also known as stochastic effects... » read more

Choosing The Right Interconnect
By Ed Sperling - 09 Apr, 2018 - Comments: 3

Efforts to zero in on cheaper advanced packaging approaches that can speed time to market are being sidetracked by a dizzying number of choices. At the center of this frenzy of activity is the [getkc id="36" kc_name="interconnect"]. Current options range from organic, silicon and glass interposers, to bridges that span different die at multiple levels. There also are various fan-out approach... » read more

The Problem With Spin-On Carbon Materials
By Runhui Huang - 09 Apr, 2018 - Comments: 0

In an integrated circuit manufacturing process, spin-on-carbon (SOC) materials constitute an important layer for the multilayer process to achieve smaller feature size. The SOC layer responds to the photolithography, pattern transformation, substrate planarization, and a variety of other critical processes. A key challenge in selecting a suitable material is that some processes require a hig... » read more

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